Electrical computers and digital processing systems: processing – Instruction fetching
Reexamination Certificate
2006-10-17
2006-10-17
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction fetching
Reexamination Certificate
active
07124281
ABSTRACT:
Embodiments of the present inventions relate to processors having sequential address indicator signals, also referred to as sequence signals, for indicating when accessed addresses are sequential. One embodiment relates to a processing system for accessing memory having an address bus for providing a current address and a previous address to memory, a data bus, an execution unit, and a decode control unit. The processing system further includes a fetch unit, coupled to the execution unit, the decode control unit, the address bus, and the data bus, for generating a first sequence signal that when negated indicates that the current address may not be sequential to the previous address, a second sequence signal that when negated indicates that the current address is not sequential to the previous address, and a third sequence signal that when negated indicates that the current address, if it is an instruction address, is not sequential to the previous address that was an instruction address.
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Moyer William C.
Murdock Brett W.
Scott Jeffrey W.
Chan Eddie
Chiu Joanna G.
Clingan, Jr. James L.
Freescale Semiconductor Inc.
Huisman David J.
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