Processing system having improved bi-directional serial clock co

Details Processing system having improved bi-directional serial clock co Processing system having improved bi-directional serial clock co

1996-12-16

1999-10-12

Maung, Zarni

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

Least weight routing

710110, 713400, 713500, 713600, G06F 1100

Patent

active

059648457

DESCRIPTION:

BRIEF SUMMARY
1 BACKGROUND OF THE INVENTION

1.1 Field of the Invention
Within a processor system consisting of a multitude of functional components encompassing at least one processing unit (PU), also called a CPU, and a clock component the present invention relates to a communication circuitry for connection and data exchange between the clock component and the PU components.
1.2 Description and Disadvantages of Prior Art
A processor system typically consists of various functional components. Depending on the type of requirements and limitations these functional components may be integrated within a single chip or may be dispersed over several separate chips. Due to silicon real estate constraints, many micro-processors do not consist of a single chip, but a chip set. Major components, as a rule, are the basic CPU component, the memory management unit component, a floating point coprocessor component, and a bus adapter component. Mainframe architectures often also includes a separate clock component, a specialized high speed control store component, a memory controller component and a specific service processor component (SP).
The machine cycle is the basic unit of timing in a computer. Within a machine cycle atomic operations, e.g. performing an addition, take place. Instructions are executed within one or several machine cycles. The machine cycle is controlled by an external timing source, an oscillator (usually a crystal) with a constant frequency. Clock logic uses this input to generate various timing signals to control the processor logic at desired timing points within the machine cycle. Existing microprocessor designs implement the clock logic function in one of two different ways: component), floating point processor component etc. components
A typical example of the second approach are IBM/390 processors implementing the IBM/390 mainframe architecture described in the "System/390 Principles of Operation". As those portions of the system that run synchronously may span several chips, the design of the clocking system deserves special attention. If clock signals are distributed over several chips the individual chips may be drastically different with regard to process tolerances. Thus the same clock signal may arrive at the receiving logic spread out in time, referred to as clock skew. A centralized clock component, together with a carefully designed topology for clock signal wiring, significantly reduces clock skew. In addition to the clock generation the clock component performs run control operations, i.e. functions like Start--Stop control, Power on reset recognition, Reset sequence generation for other components, clock checking, and Console key controls.
The clock component generates centrally all the clock signals required by the other components in the system. It requires an external hybrid oscillator and optionally an active delay line. It offers a multitude of different clock signals. The timing of each clock is independently programmable in terms of pulse width, phase, and cycle time, and thus can be adapted to the varying system requirements. The clock signals feed directly the receiving components without any further gating. All clock lines are point to point nets, and clock skews are to be minimized. Clock signals are checked within the clock component.
On power-on recognition the clock component is initialized and clock signal generation starts. The clock signals to be delivered at certain reset and start up points are controlled by the run control.
The clock component is the master of the component set for the reset function, which typically include "Power on Reset", "Reset for IML", "System Reset", "Check Reset", "Start after Reset" and so forth.
The clock component typically provides further external hardware interfaces, implemented in IBM/390 systems as a five-line support bus of two bit lines (in/out) and three control lines, to cause the clock component to execute functions mentioned above. For instance an auxiliary processor, the so-called service processor (SP), may exploit this external

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