Processing system and method including lock buffer for controlli

Details Processing system and method including lock buffer for controlli Processing system and method including lock buffer for controlli

1991-05-30

1993-08-17

Fleming, Michael R.

Boots, shoes, and leggings

395425, 3642281, 3642283, 3642401, 3642466, 3642468, 364DIG1, G06F 1214, G06F 1516

Patent

active

052376940

ABSTRACT:
There is described a system and method for use in a processing system of the type including a plurality of processor subsystems, each processor subsystem including a processor, and being coupled together and to a shared memory by a common bus, wherein the system and method permits exclusive execution of critical sections by each of the processors. A lock buffer associated with each of the processors caches the value of the interlock variable and a control section locally tests the stored interlock variable value responsive to an instruction from its processor. If the control section determines that the interlock variable has the available value, it causes the available value of the interlock variable to be conveyed to its associated processor and the busy value to be written to the local lock buffer and over the common bus to the shared memory under a write-through policy and for updating each lock buffer associated with the other processors under a write-update policy. When its processor completes its critical section, the control section causes the available value of the interlock variable to be written to the local lock buffer and over the common bus to the shared memory so that the other lock buffers update their stored values of the interlock variable to the available value.

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