Processing packet sequence using same function set pipelined...

Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...

Reexamination Certificate

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C718S107000

Reexamination Certificate

active

11092366

ABSTRACT:
A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes processing a sequence of packets with a sequence of threads, with the sequence of threads spanning multiple programmable processing elements integrated within a processor, and with the programmable processing elements providing multiple threads of execution such that each of the threads acquires exclusive modification access to data shared.

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