Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
1997-07-15
2004-03-09
Rao, Andy (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C375S240250
Reexamination Certificate
active
06704356
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a signal processing apparatus, and more particularly to an improvement of recording or reproducing apparatus for a digital video tape recorder (D-VTR) for discrete cosine transforming (DCT) video signal in order to compress amount of information thereof and recording it.
BACKGROUND ART
Heretofore, as this type of D-VTR, there is one shown in FIG.
1
. In
FIG. 1
,
1
generally denotes the D-VTR. A digital video signal S
1
(FIG.
2
(B)) input from a predetermined video signal generating unit is input to a DCT shuffling circuit
2
. The DCT shuffling circuit
2
has a DCT address circuit
3
in association therewith, a vertical synchronizing signal S
V
(FIG.
2
(A)) is input to the DCT address circuit
3
.
Accordingly, the DCT shuffling circuit
2
divides the digital video signal S
1
into DCT blocks of 8 columns×4 rows for each one field by shuffle address generated by the DCT address circuit
3
on the basis of the vertical synchronizing signal S
V
. The DCT shuffling circuit
2
collects 10 blocks of the DCT blocks from their respective positions discretely located from each other within a screen to generate shuffle data S
2
(FIG.
2
(C)), and outputs the shuffle data S
2
to the following DCT conversion circuit
4
.
Here, the DCT shuffling circuit
2
performs shuffling processing by each one field. Thereby, the shuffle data S
2
output from the DCT shuffling circuit
2
is supplied to the DCT conversion circuit
4
at a timing delayed by one field time period T
2
from the digital video signal S
1
as shown in FIG.
2
(C).
The DCT conversion circuit
4
performs discrete cosine transform to data of each DCT block and supplies DCT data S
3
to a quantization delay circuit
5
and a quantization level detecting circuit
6
. The quantization level detecting circuit
6
detects a quantization level (quantization width) for achieving a target compression rate for the DCT data S
3
. Since, at this time, about ten-block time period is required as the signal processing time in the quantization level detecting circuit
6
, the quantization delay circuit
5
delays the DCT data S
3
by the signal processing time, and supplies it to a quantization circuit
7
as a quantization delay output data S
5
. Accordingly, the quantization delay output data S
5
is input to the quantization circuit
7
at the same timing as quantization level data S
4
which is output from the quantization level detecting circuit
6
at a time point t
3
delayed by a 10-block time period T
3
from the shuffle data S
2
as shown in FIG.
2
(D).
The quantization circuit
7
quantizes the quantization delay output data S
5
supplied from the quantization delay circuit
5
based on the quantization level data S
4
supplied from the quantization level detecting circuit
6
in order to compress amount of information thereof. At this time, the quantization circuit
7
detects a maximum value, a minimum value, and a mean value etc., of quantization level within one field, on the basis of a period signal for each one field obtained from the vertical synchronizing signal S
V
at a vertical counter
8
provided in association therewith, and outputs the result as detection data S
6
to a quantization monitor (not shown) to monitor the state of compression of data at the quantization circuit
7
.
Further, quantization data S
7
obtained from the quantization circuit
7
is supplied to a variable-length coding circuit
9
. The variable-length coding circuit
9
performs variable-length coding to the quantization data S
7
to generate variable-length coding data S
9
having a block length prescribed in a format, and outputs it to an error correcting outer coding circuit
11
.
The error correcting outer coding circuit
11
generates an error correcting outer code for correcting an error occurred in the manner of a burst, on the basis of a timing obtained from the vertical synchronizing signal S
V
at a parity timing circuit
12
which is provided in association therewith, and the result is added to the variable-length coding data S
9
and is output to a track shuffling circuit
13
.
The track shuffling circuit
13
generates track shuffle data S
13
by recording the data into an order suitable for the track pattern on a magnetic tape, in accordance with shuffle address obtained from the vertical synchronizing signal S
V
at a track address circuit
14
which is provided in association therewith.
The track shuffle data S
13
is supplied to an error correcting inner coding circuit
15
. The error correcting inner coding circuit
15
generates an error correcting inner code for correcting random error and adds to the track shuffle data S
13
. An ID counter
16
which is provided in association with the error correcting inner coding circuit
15
, obtains a block number obtained from the vertical synchronizing signal S
V
and the color field signal S
C
, and color field information corresponding to a time period when the phase shift of carrier resulting from phase shifts by each scanning line completes a cycle.
The error correcting inner coding circuit
15
adds the block number and the color field information to the track shuffle data S
13
as ID information, and outputs the result to a recording circuit
17
as recording data S
12
. The recording circuit
17
converts the recording data S
12
from an 8 [bit] parallel form to 1 [bit] serial form and effects channel coding suitable for magnetic recording, and records on a magnetic tape
19
by means of a magnetic head
18
provided on a rotary drum.
Here, since the track shuffling circuit
13
performs re-ordering processing of data by each ⅓ field, the recording data S
12
obtained on the basis of the track shuffle data S
13
is output from the error correcting inner coding circuit
15
at a time point t
4
delayed by ⅓ field period T
4
from quantization delay output data S
5
output from the quantization delay circuit
5
as shown in FIG.
2
(E).
Here, in the recording data S
12
in the D-VTR
1
, a synchronizing pattern is added to the beginning of a data block as a delimiter for the block and a delimiter for restoring data recorded in 1 [bit] serial form on the magnetic tape into the original 8 [bit] parallel form.
Further, a block number for indicating the sequential order of each data block is added as ID information at the error correcting inner coding circuit
15
, so that an image is reproduced even when data blocks are not continuously reproduced as the reproducing head helically scans a plurality of tracks in double-speed reproducing etc. Furthermore, color field information is also added as ID information at the error correcting inner coding circuit
15
.
Further, video data generated through the above DCT shuffling circuit
2
to the error correcting inner coding circuit
15
is recorded subsequently to the ID information. At the beginning of the video data, the quantization level information in data compression is added at the quantization circuit
7
in accordance with the quantization level data S
4
. Furthermore, an inner parity data for correcting a random error is added at the error correcting inner coding circuit
15
.
In the D-VTR
1
of such construction, data is output with a delay of the time necessary for the signal processing at each signal processing circuit. For example, at the DCT shuffling circuit
2
, data is output with a delay corresponding to one field time period T
2
(FIG.
2
(C)), and at the quantization delay circuit
5
, data is delayed by 10-block time period T
3
(FIG.
2
(D)). Further, at the DCT conversion circuit
4
, the quantization circuit
7
, and the variable-length coding circuit
9
, data is delayed by about one block time period respectively, and at the track shuffling circuit
13
, data is delayed by ⅓ field time period T
4
(FIG.
2
(E)).
Accordingly, at the timing circuits of the vertical counter
8
, the parity timing circuit
12
, the track address circuit
14
, and the ID counter
16
, timing signals mus
Frommer William S.
Frommer & Lawrence & Haug LLP
Rao Andy
Sony Corporation
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