Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-12-23
2003-08-26
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06611856
ABSTRACT:
BACKGROUND
This invention relates to processor-based systems and, more particularly, to multiply-accumulate units.
A multiply-accumulate unit, or MAC, is a unit designed to perform multiplication operations. In a processor-based system, for example, such operations may be plentiful.
MACs may be implemented using a variety of logic. Because of the abundance of multiplication operations in some applications, the fastest performing MAC is generally preferred. The success of any MAC design may depend upon the power requirements, the available space which may be allocated to MAC circuitry, and the intended use for the MAC, among other considerations.
Usually, however, a tradeoff between speed and cost makes the design of an optimally performing MAC difficult. The cost may come in the form of additional hardware, the chip space necessary to accommodate that hardware, or in the power needed to drive the hardware.
For example, in many digital signal processing, or DSP, applications, some critical operations may involve a series of multiplications and or accumulations. Accordingly, a high-throughput MAC is essential to achieving high performance. However, many DSP applications today require low power consumption, particularly in the portable electronics market.
Thus, there is a continuing need for a MAC which may achieve high throughput without excessively consuming power.
SUMMARY
In one embodiment of the invention, a method includes receiving a first set of operands in a first portion of a unit, performing a plurality of operations on the first set of operands to arrive at a first intermediate result and receiving a second set of operands in the first portion of the unit. Following these, a second plurality of operations is performed on the first intermediate result to arrive at a first final result while the first plurality of operations is performed on the second set of operands to arrive at a second intermediate result.
Advantages and other features of the invention will become apparent from the following description, the drawings, and the claims.
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Hameenanttila Tom M.
Liao Yuyun
Roberts David B.
Mai Tan V.
Trop Pruner & Hu P.C.
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