Processing microchips

Fishing – trapping – and vermin destroying

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Details

437183, 437187, 437203, H01L 2160

Patent

active

054119189

DESCRIPTION:

BRIEF SUMMARY
This invention relates to processing of integrated circuit semiconductor devices and in particular, to a method of providing such devices, for example an integrated circuit semi-conductor chip, with projecting electrically conductive material on the device bonding sites.
A known method of providing vertical interconnection between the bonding pads of an integrated circuit chip and bonding sites of an associated package is the "flip chip" technique described, for example, in EP-A-0186818. In that technique, solder balls are provided on the input/output bonding pads of the chip, which are accessible through apertures in the 1-2 micrometers thick passivation layer normally covering the chip surface. That technique suffers from the problem that small solder balls or "bumps" tend to provide inadequate tolerance to thermal expansion stresses owing to their small height and resulting low degree of compliance, whereas larger solder balls introduce limitations on the closeness of pad spacing. The present invention provides a modified "flip chip" in which these problems are alleviated.
The invention accordingly provides a method of providing an integrated circuit semiconductor device with electrically conductive material projecting from the device bonding sites for bonding to a matching array of electrical contacts with which the device will be face-to-face in use, comprising (a) providing an electrically insulating layer at least 5 micrometers thick adhering to the surface of the device with one or more holes through the insulating layer each communicating with a bonding site. (b) depositing electrically conductive material within the hole(s) to establish electrical connection to the bonding site(s), and (c) excluding, or if necessary removing, deposited conductive material from the main surface of the insulating layer, so as to provide the conductive material substantially only within the said hole(s).
At first sight, it was not clear that a perforating operation could be successfully earned out in situ on the surface of the device, especially a microchip, without damaging the relatively delicate underlying bonding sites and nearby circuitry. However, it has proved possible to control the perforating operation so as to avoid damaging the bonding sites, as hereinafter described, even when the perforation is at least partly effected by the preferred high efficiency and high precision technique of ultraviolet laser ablation, preferably using an excimer laser at wave lengths of 193 (ArF), 308 (XeCl), or preferably 249 (KrF) nanometers. Other perforation techniques, for example reactive ion etching, or chemical etching could be used, but excimer laser ablation is preferred for its high speed and ability to perforate thick layers, possibly together with a final chemical etching step as hereinafter described.
It was also not expected to be possible to plate into one-ended "blind" holes of the diameters and depths preferred for this invention, but this has also been achieved, for example with hole diameters in the range of 5-200 micrometers, preferably 15-100 micrometers, and especially 25-50 micrometers.
After the deposition of the electrically conductive material, the method preferably includes the step of removing some or all of the insulating layer to expose at least part of conductive material deposited within the holes. In this way, projecting electrically conductive material taller than the known solder balls can be provided on chip bonding sites for subsequent connection to chip packaging arrangements.
When using the preferred laser ablation perforating technique, it is theoretically possible to limit the number of laser pulses or "shots" to drill exactly through the insulating layer adhering to the device surface and overlying the bonding sites, without damaging the underlying sites themselves. However, in practice, this can be difficult owing to slight fluctuations in the thickness of the insulating layer and/or to variations in the light flux actually reaching the insulating surface to be ablated, for example o

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Journal of Vacuum Science & Technology-Laser ablation of polymers, J. T. C. Yeh, May-Jun. 1986, pp. 653-658.
Journal of the Electrochemical Society-Selective Electroless Metal Deposition for Via Hole Filling in VLSI Multilevel Interconnection Structures, C. H. Ting etal, Feb. 1989, pp. 462-466.

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