Processing methods of forming an electrically conductive plug to

Details Processing methods of forming an electrically conductive plug to Processing methods of forming an electrically conductive plug to

1997-02-28

1999-02-16

Brown, Peter Toby

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

438253, 438397, H01L 2170

Patent

active

058720480

ABSTRACT:
Methods of forming electrical connections with an integrated circuitry substrate node location are described. According to one aspect of the invention, a substrate node location is laterally surrounded with insulating material and left outwardly exposed. Conductive material is deposited over the exposed node location. Subsequently, a photomaskless etch of the conductive material is conducted to a degree sufficient to leave a plug of conductive material over the node location. In a preferred implementation, the insulating material with which such node location is surrounded constitutes insulating material portions which are provided relative to conductive lines which are formed over the substrate. In another preferred implementation, such conductive lines form a grid of insulating material which, in turn, defines the node location. According to a preferred aspect of the invention, a plurality of insulated conductive lines are formed over a substrate. At least some of the conductive lines constitute word lines and at least some of the conductive lines constitute bit lines. The lines are preferably formed to define and laterally surround an active area substrate location. The substrate location is preferably surrounded by at least four of the lines. Conductive material is deposited over the substrate and the conductive lines and in electrical contact with the node location. The conductive material is then removed to a degree sufficient to form an isolated plug of conductive material over the node location and between the four conductive lines.

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M. Sakao, N. Kasai, T. Ishijima, E. Ikawa, H. Watanabe, K. Terada and T. Kikkawa, "A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64mb DRAMs," Microelectronics Research Laboratories, NEC Corporation, 1990, pp. 27.3.1-27.3.4.

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