Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-08-30
2003-07-08
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000, C438S759000
Reexamination Certificate
active
06589871
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a processing method suitable for processing of a semiconductor substrate or the like, a measuring method and a method of producing a semiconductor device.
In a producing process for a semiconductor device of a high integration degree such as a DRAM (Dynamic Random Access Memory) having an integration degree of 256 Mbits or more, a fine pattern with a minimum size of 0.2 &mgr;m or less is formed. When such a fine pattern is formed with a high accuracy by using photolithography, it is necessary to make the wavelength of exposure light shorter and increase the numerical aperture. Correspondingly, an allowable focal depth of a reduction projection exposure system used for the photolithographic step becomes shallower. For exposure and transfer of a fine circuit pattern at a high resolution to a photosensitive film (photoresist film) on a thin film formed on the surface of a substrate in the photolithographic step, a flatness of 0.3 &mgr;m or less is required for the film of the photosensitive surface as an exposed surface.
To obtain the flatness on the surface of the photosensitive film, Japanese Patent Laid-Open Hei 7-314298 discloses a reflow flattening method of softening to reflow an insulation film as an underlayer for forming the photosensitive film. Further, there are known an etching method of dissolving to flatten convex portions on an insulation film and a chemical mechanical polishing method (CMP) of fabricating an insulation film mechano-chemically by using a slurry containing an abrasive as a processing liquid and a polishing pad.
The existent reflow fattening method or etching method can locally smooth stepped portions but has no consideration in that a degree of flatness to satisfy an allowable range of a shallow focal depth of an exposure device cannot be obtained over a wide region of a semiconductor substrate (diameter of 300 mm or more). The chemical mechanical polishing method has been introduced in recent years in the semiconductor producing process as a technique capable of obtaining better flatness compared with the reflow flattening method. The chemical mechanical polishing method is adapted to polish the surface of a substrate by pressing a soft polishing cloth (a polishing pad made of polyurethane having a longitudinal elastic coefficient of 1000 kg/cm
2
or less) as a polishing member to a thin film surface formed on the surface of a substrate. In this method, as the pressing force of the polishing member to the semiconductor substrate is larger, that is, as the processing surface pressure is higher, flatness on the surface of the substrate after fabrication is worsened. However, when the fabrication surface pressure is lowered to reduce the phenomenon of worsening flatness, the processing efficiency is lowered to increase the processing time and lower the throughput. Further, no consideration has been taken in that the flatness of the substrate surface after processing is lowered due to the pressing force to the substrate surface or aging change of the polishing pad surface.
On the other hand, Japanese Patent Laid-Open Hei 9-232260 discloses a technique of processing the substrate surface by using a abrasive plate (fixed abrasive particle disk) in which polishing abrasive particles are compacted by a resin instead of using the polishing agent and the polishing cloth. Since the abrasive plate is harder compared with the polishing cloth (for example, having longitudinal elastic coefficient of 5000 kg/cm
2
or more), the flattening performance for the substrate surface in a circuit pattern region of an unevenned shape has been improved but it requires time and labor to optimize the countermeasure to reduce a so-called edge sagging in which the processing characteristics for the outer peripheral surface of the substrate is not uniform and, further, no consideration has been taken in that forecasting of aging change is difficult.
As an example for the countermeasure reducing the edge sagging, Japanese Patent Laid-Open Hei 6-155286, for example, discloses a method of preventing excessive polishing for the outer periphery of a wafer by disposing an inclined surface to the structure of the inner wall surface of a guide formed to the outer periphery of the wafer and the publication discloses data showing the effect thereof. However, the data showing the effect are discontinuous such as 3, 5 and 10 degree of angle of inclination, so that optimal conditions or allowable range are not clear and it has no consideration in that labor and time are required for optimization in a case where a user mass produces semiconductor devices in an actual production line at high reliability and yield.
The present inventors have examined the correlation for a plurality of measuring data of in-plane distribution in the step of producing semiconductor devices, estimated the in-plane distribution characteristics for an unknown processing conditions in comparison with the correlation function of known data and have experimentally found for the first time that an optimum processing condition can be presented.
Further, although not regarding the polishing method, Japanese Patent Laid-Open Hei 5-270973 discloses a technique, to determine the processing condition based on the comparison with the known correlation function of data, of measuring the in-plane resistivity in the transverse cross section of a single crystal rod with respect to a plurality of different magnetic field intensities respectively for making the distribution uniform for the resistivity in the plane of the silicon wafer and determining the magnetic field intensity with a small distribution of the in-plane resistivity based on the correlationship. However, this invention has no consideration on the determination of an estimate value with a fine accuracy.
OBJECT OF THE INVENTION
At first, this invention intends to provide a processing method capable of presenting a processing condition with a high accuracy and improving the productivity.
Secondly, this invention intends to provide a method of producing a semiconductor device capable of presenting a processing condition with a high accuracy and improving the productivity.
Thirdly, this invention intends to provide a measuring method for obtaining products with a high accuracy.
SUMMARY OF THE INVENTION
To attain the first object, the processing method according to this invention comprises:
a step of applying a first processing to a first substrate;
a step of applying a second processing to the first substrate or applying the second processing to a second substrate;
determining a correlation function for each of in-plane positions as data for the difference in a plurality of processing steps for each of in-plane positions, based on the in-plane distribution data for the in-plane position of each of the substrates as the result of the plurality of processings;
calculating the in-plane distribution characteristics of a substrate under a desired processing condition in view of the correlation function; and
processing the substrate based on the in-plane distribution characteristics.
Further, To attain the first object, the processing method according to this invention comprises:
a step of applying a first processing to a first substrate;
a step of applying a second processing to the first substrate or applying the second processing to a second substrate;
determining a correlation function for each of in-plane positions as data for the difference in a plurality of processing steps for each of in-plane positions, based on the in-plane distribution data for the in-plane position of each of the substrates as the result of the plurality of processings;
calculating the in-plane distribution characteristics of a substrate under a desired processing condition in view of the correlation function; and
processing the substrate in view of the in-plane distribution characteristics, based on the processing condition to provide minimum uniformness.
Processing based on the processing condition to provide minimum uniformness does not always
Katagiri Souichi
Kawamura Yoshio
Nagasawa Masayuki
Yamaguchi Ui
Yasui Kan
Thomas Toniae M.
Zarabian Amir
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