Electrical computers and digital processing systems: processing – Architecture based instruction processing
Reexamination Certificate
1999-11-18
2001-10-23
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
C712S215000, C712S247000
Reexamination Certificate
active
06308254
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of processors. More specifically, the present invention relates to the art of implementing instruction set architectures (ISA) on these processors and controlling the datapaths of these processors.
2. Background Information
Every processor has an ISA. The term processor as used herein is intended to include micro-controllers (MCU), digital signal processors (DSP), general purpose microprocessors, and the like, whereas the term ISA as used herein refers to the aspects of a processor that are visible to a programmer or compiler writer. The ISA of the various processors known in the art can be differentiated by the type of internal storage provided by the processor for instruction operands, the number of explicit operands named per instruction, whether instruction operands can be located outside the processor, the various operations provided, the type and size of the operands, and so forth.
Historically, implementation of an ISA is accomplished through the control logic provided to a processor to control the processor's datapath in performing arithmetic logic operations, which is typically specific for the ISA to be implemented. The term datapath as used herein is intended to be a collective reference to the processor elements employed in performing arithmetic logic operations. In the case of prior art processors, the datapath typically includes arithmetic logic unit(s) (ALU), operand register file, various control registers and so forth. The control logic is provided either through hardwired logic or microprogramming (also referred to as microcode or firmware). In the case of hardwired logic, typically one or more random control logic block are employed to generate the proper control signals to be output to control the datapath. The proper control signal to be output at a particular clock cycle is selected based on the current state of the processor, feedback from the datapath and the opcode of the next instruction to be executed. In the case of microprogramming, typically microinstructions are employed to specify the control signals for the datapath. The microinstructions are stored e.g. in a read-only-memory (ROM), and selected for output in each clock cycle, based on the current microinstruction program counter (PC). At each clock cycle, the microinstruction PC is modified based on a newly computed next microinstruction PC, the current microinstruction output (specifying in part the next microinstruction to be output), feedback from the datapath, and/or the opcode of the next instruction to be executed (also referred to as the next macroinstruction).
Some prior art successor processors, for legacy reasons, would accept complex instruction set computer (CISC) instructions of an historic ISA, and decode them into reduced instruction set computer (RISC) instructions of a new internal ISA for execution, even though the processors are designed with more modern RISC principles. Typically, the new internal ISA is designed to specifically mimic the historic ISA. The processor is provided with a decoder to handle the conversion between the two architectures, and control logic is equipped to control the datapath to specifically implement the new internal ISA. Instructions of the internal ISA are issued to the datapath using a micro-instruction program counter.
These prior art approaches to implementing an ISA and controlling a processor's datapath suffer from a number of disadvantages. First and foremost, each processor is capable of executing only one ISA. Much of the control logic of a processor would have to be redesigned if the processor is to be adapted to support a different or a new ISA. Except for enhancements and extensions to an existing ISA, the industry almost never adapt a processor to support a different or a new processor, because of the amount of redesign effort would have been required. Virtually all processors supporting a new ISA are considered to be new designs. As a result, the industry is often confronted with significant conversion effort to adopt a more powerful new processor, executing a new ISA, to replace a number of less powerful older processors, executing their respective old ISA. Alternatively, the conversion effort becomes a significant roadblock to the wider acceptance or deployment of the more powerful new processor. For example, in many applications it is actually more price/performance effective to use anyone of a number of newer general purpose microprocessors, then to continue to use an older DSP in combination with an older MCU, but for the conversion cost of the legacy code.
Thus, a more effective approach to ISA implementation and controlling a processor's datapath without some of the prior art disadvantages is desired.
SUMMARY OF THE INVENTION
A new approach to implementing an ISA is disclosed. A processor is provided with a datapath and control logic to control the datapath to selectively execute a number of hierarchically organized primitive operations to effectuate execution of user instruction streams constituted with instructions of the ISA. In one embodiment, primitive operations are statically organized into atomic units, which in turn are statically organized into snippets of execution threads. Selected ones of the snippets are logically associated together to form execution threads, which collectively implement the instructions of the ISA.
In one embodiment, the execution of an atomic unit may be conditional, depending on whether certain associated execution conditions are met or not. The associated execution conditions are specified as a part of the snippet to which an atomic unit is a member. Additionally, the snippets are logically associated, using trap requests to the control logic.
During operation, the control logic selectively schedules the various execution threads for execution by the datapath, starting with the first snippets of the execution threads, responsive to instructions of user instruction streams. Within each execution thread, the control logic dynamically schedules additional ones of the associated snippets for successive execution, responsive to trap requests from the predecessor snippets to the control logic. For each scheduled snippet, the primitive operations of each atomic unit are issued in order to the datapath to be conditionally executed.
In one embodiment, the datapath includes an ALU and a cache memory operated to directly supply and accept operand values to and from the ALU. The ALU and the cache memory respond to the controls of the control logic as it selectively provides the atomic units of primitive operations for conditional execution.
In one embodiment, the processor is further provided with an ISA library to store the various execution threads employed to implement the instructions of an ISA. The control logic is further equipped with one or more primitive operation cache to selectively cache the implementing threads.
In one embodiment, the ISA library stores the implementing threads of multiple ISA, with the different implementing threads for the different ISA to be used in different deployments of the processor. In another embodiment, the different implementing threads for the different ISA are used for different applications interleavingly. In yet another embodiment, the different implementing threads for the different ISA are used for different applications in parallel.
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Blakely , Sokoloff, Taylor & Zafman LLP
Brecis
Kim Kenneth S.
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