Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2007-08-09
2010-12-14
Kim, Kenneth S (Department: 2111)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S205000
Reexamination Certificate
active
07853775
ABSTRACT:
Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the PEs, where P<S, operate as an instruction cache. The remaining memories operate as data memories or as data cache memories. One out of S sets of general-purpose registers, inherently belonging to the PEs, directly operates as a general register group for the PU. Out of the remaining S−1 sets, T set or a required number of sets, where T<S−1, are used as storage registers that store tags of the instruction cache.
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Chinese Official Action dated Dec. 11, 2009 together with Japanese Translation and English Translation.
Kim Kenneth S
NEC Corporation
Scully , Scott, Murphy & Presser, P.C.
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