Processing devices with improved addressing capabilities, system

Details Processing devices with improved addressing capabilities, system Processing devices with improved addressing capabilities, system

1995-04-10

1998-05-12

Lane, Jack A.

3954211, 395800, 395384, G06F 934

Patent

active

057519919

ABSTRACT:
A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.

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