Processing communication system having a plurality of memories a

Details Processing communication system having a plurality of memories a Processing communication system having a plurality of memories a

1993-02-02

1993-09-28

Anderson, Lawrence E.

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395375, 395425, 364DIG1, 364DIG2, 3642319, 3642322, 36423221, 36493101, 36493143, 3649314, 36493151, G06F 1516, G06F 15347

Patent

active

052493016

ABSTRACT:
The invention is in the realm of an information processing system including a central unit which includes several processors sending requests to several processors sending requests to several memories via an input interconnection and receiving responses from those memories via an output interconnection. To simplify the input interconnection when the number of processors and memories increases, a ring of stations equipped with a register is used. A request given by a processor is loaded into a station when that station is free or becomes free, If not the ring functions a fed back shift register. A station becomes free when the request contained in the station downstream is accepted by a memory. An analogous device can be used for the output interconnection. A notable application is vector processing.

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Computer Architecture and Parallel Processing, Hwang et al. 1984.

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