Coded data generation or conversion – Digital code to digital code converters – To or from variable length codes
Reexamination Certificate
2002-10-25
2003-07-01
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from variable length codes
C341S065000
Reexamination Certificate
active
06587058
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to image processing circuits and techniques, and more particularly to a processing circuit and method for the variable-length coding and encoding of data such as video data.
BACKGROUND OF THE INVENTION
Variable-length codes are used to encode many types of data. For example, the popular block-based Motion Picture Experts Group (MPEG) video compression standard encodes video data as variable-length symbols for transmission or storage. In addition, many types of variable-length codes, such as Huffman codes, are lossless.
Typically, variable-length encoded data is transmitted serially. Therefore, the transmission, reception, and decoding of such data are relatively time consuming as compared with data that can be transmitted, received, or decoded in parallel.
To decrease the transmission, reception, and decoding times, circuit hardware has been developed to process such data. That is, the architecture of such hardware is configured to efficiently implement the variable-length decoding or encoding process. A problem with such hardware, however, is that it is typically designed for a specific type of variable-length code. Therefore, hardware designed to encode or decode data according to one type of variable-length code may be inefficient or unable to encode or decode data according to another type of variable-length code. But many bit streams such as some MPEG bit streams include bit segments that are respectively encoded according to different variable-length codes. Therefore, decoding hardware often must include multiple circuits each designed to decode bit segments according to a respective variable-length code. Unfortunately, this often increases the size, complexity, and cost of the decoding hardware.
Another alternative is to program a processor to perform the variable-length encoding or decoding. Therefore, for bit streams using more than one variable-length code, one can change the processor software “on the fly,” and thus perform all of the encoding or decoding with a single processor. Unfortunately, because the architectures of most processors are not optimized for variable-length encoding or decoding, such processors are relatively slow when variable-length encoding or decoding data. Therefore, it is often difficult or impossible for such processors to variable-length encode or decode data in real time.
SUMMARY OF THE INVENTION
In one aspect of the invention, a variable-length encode/decode processor includes a central processing unit, and includes an instruction buffer and a getbits processing engine coupled to the central processing unit. Such a processor can be used to encode data as variable-length symbols or to decode variable-length symbols such as those found in an MPEG bitstream.
Data compression schemes such as Huffman encoding use variable length codes (VLCs). Video compression standards such as MPEG use VLCs; for example, the following are legal MPEG codes:
‘00’
‘01’
‘110’
‘000000000000000000000001’
In a stream of these types of symbols, the second symbol in the stream cannot be decoded until the length and semantics of the first is known. This is an inherently serial process that can be efficiently performed by a dedicated small programmable engine.
For this reason, a video processor such as the Map1000 processor benefits from inclusion of a “VLx processor”, an engine dedicated to the processing needs of variable-length data such as that within an MPEG stream. The VLx processor allows flexibility in the processing of incoming bitstreams and in how that information about that bitstream is relayed back to the Map1000. Efficient processing has been achieved by designing the hardware to minimize critical loops in processing variable length data and to save memory by using a compressed set of tables.
The general design intent was to fulfill the following requirements:
Handle a High Definition Television (HDTV) MPEG stream at 19.4 MBits/sec into an 8 MBit Video Buffering Verifier (VBV) buffer.
Generate decimated coefficients to display HDTV at MP@ML resolutions
Simultaneously handle encoding and decoding of Main Profile at Main Level (MP@ML) streams
For a task such as the decoding of HDTV MPEG streams, the VLx processor might perform the following types of activities based on the program that it executes:
Preprocess an MPEG stream to build structures that define the content of the stream
Decode Discrete Cosine Transform (DCT) coefficients
Create an MPEG stream
The VLx processor is fed bitstreams by Map1000 tasks in one of two ways. It can process data that is placed in the Coprocessor Memory Bank, or it can take input bitstreams through I/O channels that are fed by the Map1000 Data Streamer unit.
The resultant information, decimated bitstreams, or newly constructed streams are transferred back to the MAP1000 through memory transfers or as I/O output bitstreams.
The VLx processor consists of a simple processing engine, a set of dedicated registers, a GetBits engine for handling bitstreams and I/O interactions, optimized access to the FFB for Coprocessor Memory
1
(CM
1
) access and a way to issue a DsContinue( ) operation to the Data Streamer.
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patent: 5821887 (1998-10-01), Zhu
patent: 5831557 (1998-11-01), Handley
patent: 5857088 (1999-01-01), Keith et al.
Berekovic et al.,A Multimedia RISC Core for Efficient Bitstream Parsing and VLD,Proceedings of SPIE Multimedia Hardware Architectures 1998, vol. 3311 Jan. 1998, San Jose, Ca., pp. 131-142.*
Iwata et al., ISSCC '97 “A 2.2GOPS Video DSP with 2-RISC MIMD, 6-PE SIMD Architecture for Real-Time MPEG2 Video Coding/Decoding”, IEEE 1997 International Solid State Circuits Conference Tech. Papers, pp. 258, 259 & 469.
Yamada et al., “Real-Time MPEG Encoding and Decoding with a Dual-Issue RISC Processor”, IEEE 1997 Custom Integrated Circuits Conference, pp. 225-228.
Deeley Richard M.
Lee Woobin
Mundkur Yatin
Equator Technologies Inc.
Graybeal Jackson Haley LLP
Williams Howard L.
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