Processing asynchronous data within a set-top decoder

Details Processing asynchronous data within a set-top decoder Processing asynchronous data within a set-top decoder

1997-02-14

1999-09-07

Nguyen, Chau

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

348 10, 370468, H04J 306

Patent

active

059497955

ABSTRACT:
Data overflow in a buffer of a set-top decoder for receiving asynchronous data, such as digital television signals, is prevented while also maintaining compliance with an interface timing standard such as the RS404-A standard. A fullness level of the buffer is monitored to determine whether the fullness falls within a first, nominal range, or into second or third higher ranges. A clocking signal is derived from a ratio of a fixed reference clock signal and a divisor for outputting asynchronous data from the buffer at a desired rate. A direct digital synthesis (DDS) circuit may be used to provide a fractional divisor. The divisor is selected to provide the clocking signal at a rate so that a difference between a target output rate and the actual output rate falls within a data performance standard such as the RS404-A standard.

REFERENCES:
patent: 5291468 (1994-03-01), Carmon et al.
patent: 5323272 (1994-06-01), Klingler
patent: 5396492 (1995-03-01), Lien
patent: 5526362 (1996-06-01), Thompson et al.
patent: 5566208 (1996-10-01), Balakrishnan

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