Processing architecture for a reconfigurable arithmetic node

Details Processing architecture for a reconfigurable arithmetic node Processing architecture for a reconfigurable arithmetic node

2003-05-21

2008-10-07

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07433909

ABSTRACT:
A computational unit, or node, in a adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection scheme. Functionality types include the following: Asymmetric Finite Impulse Response (FIR) Filter, Symmetric FIR Filter, Complex Multiply/FIR Filter, Sum-of-absolute-differences, Bi-linear Interpolation, Biquad Infinite Impulse Response (IIR) Filter, Radix-2 Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT), Radix-2 Discrete Cosign Transform (DCT)/Inverse Discrete Cosign Transform (IDCT), Golay Correlator, Local Oscillator/Mixer.

REFERENCES:
patent: 4758985 (1988-07-01), Carter
patent: 4905231 (1990-02-01), Leung et al.
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5218240 (1993-06-01), Camarota et al.
patent: 5245227 (1993-09-01), Furtek et al.
patent: 5336950 (1994-08-01), Popli et al.
patent: 5388062 (1995-02-01), Knutson
patent: 5450557 (1995-09-01), Kopp et al.
patent: 5646544 (1997-07-01), Iadanza
patent: 5729754 (1998-03-01), Estes
patent: 5737631 (1998-04-01), Trimberger
patent: 5796957 (1998-08-01), Yamamoto et al.
patent: 5802055 (1998-09-01), Krein et al.
patent: 5828858 (1998-10-01), Athanas et al.
patent: 5889816 (1999-03-01), Agrawal et al.
patent: 5892961 (1999-04-01), Trimberger
patent: 5907580 (1999-05-01), Cummings
patent: 5910733 (1999-06-01), Bertolet et al.
patent: 5959881 (1999-09-01), Trimberger et al.
patent: 5963048 (1999-10-01), Harrison et al.
patent: 5966534 (1999-10-01), Cooke et al.
patent: 5970254 (1999-10-01), Cooke et al.
patent: 6023742 (2000-02-01), Ebeling et al.
patent: 6088043 (2000-07-01), Kelleher et al.
patent: 6094065 (2000-07-01), Tavana et al.
patent: 6119178 (2000-09-01), Martin et al.
patent: 6120551 (2000-09-01), Law et al.
patent: 6150838 (2000-11-01), Wittig et al.
patent: 6230307 (2001-05-01), Davis et al.
patent: 6237029 (2001-05-01), Master et al.
patent: 6266760 (2001-07-01), DeHon et al.
patent: 6282627 (2001-08-01), Wong et al.
patent: 6353841 (2002-03-01), Marshall et al.
patent: 6381293 (2002-04-01), Lee et al.
patent: 6408039 (2002-06-01), Ito
patent: 6426649 (2002-07-01), Fu et al.
patent: 6433578 (2002-08-01), Wasson
patent: 6483343 (2002-11-01), Faith et al.
patent: 6510138 (2003-01-01), Pannell
patent: 6675284 (2004-01-01), Warren
patent: 6694380 (2004-02-01), Wolrich et al.
patent: 6859434 (2005-02-01), Segal et al.
patent: 6941336 (2005-09-01), Mar
patent: 6980515 (2005-12-01), Schunk et al.
patent: 2001/0052793 (2001-12-01), Nakaya
patent: 2002/0042875 (2002-04-01), Shukla
patent: 2002/0138716 (2002-09-01), Master et al.
patent: 2002/0184275 (2002-12-01), Dutta et al.
patent: 2003/0074473 (2003-04-01), Pham et al.

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