Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-03-21
2001-12-25
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C257S303000, C438S622000
Reexamination Certificate
active
06333239
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to capacitor structures and, more particularly, to structures and processes for fabricating interleaved type capacitors in integrated circuit technology.
BACKGROUND OF THE INVENTION
Capacitors are an essential element in integrated circuit technology. They are used, for example, as storage nodes in dynamic random access memories (DRAMS), decoupling elements in fast switching logic chips, and filter elements in signal processing chips. Currently three main capacitor structures are used for the above mentioned applications.
One conventional capacitor structure is a planar capacitor. A typical planar capacitor is fabricated on a substrate, has an insulator layer and a conductive layer, and is known as a thin polysilicon gated capacitor. An example of a planar capacitor is described in U.S. Pat. No. 4,419,812. Formed in either the substrate or the metalization layers, planar capacitors have a drawback because they are essentially two dimensional and occupy a large area of the underlying structure.
Another capacitor structure is the trench capacitor, which is typically fabricated in the substrate. An example of a trench capacitor is described in U.S. Pat. No. 4,958,318. Conventional trench capacitors have several drawbacks. In particular, when formed in the substrate, a trench capacitor uses a significant percentage of the total processing cost and still occupies some critical area thereby decreasing the area available for other devices in the substrate, such as transistors. In addition, trench capacitors may cause dislocations in the substrate.
A third capacitor structure is the stacked capacitor, formed in the first levels of the metalization and insulator stacks. The typical stacked capacitor is formed in the first level of metallurgy and insulation in integrated circuit technology. The topography associated with stacked capacitors aggravates problems associated with forming contacts for these capacitors as well as integrating the capacitor with other connections within the substrate. Furthermore, when stacked capacitors are formed in the insulation layers above the substrate, although these capacitors may conserve active area in the substrate, this conservation results in an exaggerated three dimensional topography due to the attendant increase in the vertical dimension to achieve the necessary capacitance. Another drawback is that stacked capacitors require extensive processing steps to fabricate.
As shown in
FIG. 1
, the planar area occupied by capacitor
100
depends on the feature size F and the lithography used to define it. Thus, capacitors of minimum dimension with reduced topography and high capacitance are desired. In addition, it is desired that the size of reduced topography capacitors integrate easily into current device processing.
SUMMARY OF THE INVENTION
In view of the shortcomings of the prior art, it is an object of the present invention to form high capacitance integrated circuit elements which have minimal topography and are easily integrated into standard silicon processes.
The present invention relates to a planarized interleaved capacitor for use with a substrate comprising a plurality of planarized metal layers formed above the substrate, at least one dielectric layer disposed between the plurality of planarized metal layers, and at least one insulator layer disposed over one of the plurality of metal layers.
The present invention further relates to a process for forming an interleaved capacitor above a substrate. The process comprises the steps of disposing a first planarized insulator above the substrate and forming a first contact area in the substrate. A metal layer is then disposed in the contact area and planarized to form one plate of the capacitor. A second planarized insulator is then disposed above the first metal layer and a second contact area is formed in that layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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Aitken John M.
Strong Alvin W.
International Business Machines - Corporation
Lee Calvin
Ratner & Prestia
Smith Matthew
Townsend, Esq. Tiffany L.
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