Processes for manufacturing semiconductor devices

Details Processes for manufacturing semiconductor devices Processes for manufacturing semiconductor devices

1975-12-01

1977-09-20

Tupman, W.

Metal working

Method of mechanical manufacture

Assembling or joining

29579, 29580, 357 15, 357 23, B01J 1700

Patent

active

040487121

ABSTRACT:
A process for manufacturing MES-FET transistors with self-aligned Schottky barrier gate electrode, in which a layer of metal is deposited on a semiconductor slice, a resist geometry corresponding to the spacing of the drain and source ohmic contacts is defined, the excess metal is etched away with controlled underetching under said resist, a metal is then evaporated for forming the ohmic contacts, the metal remaining after said etching constituting the self-aligned gate electrode.

REFERENCES:
patent: 3711745 (1973-01-01), Moroney
patent: 3758943 (1973-09-01), Shibata
patent: 3813291 (1974-05-01), Joshi

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