Processes for manufacturing insulated-gate semiconductor devices

Details Processes for manufacturing insulated-gate semiconductor devices Processes for manufacturing insulated-gate semiconductor devices

1982-08-09

1983-11-29

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29579, 29580, 29591, 148187, H01L 21265

Patent

active

044173857

ABSTRACT:
Processes for manufacturing insulated-gate semiconductor devices characterized by involving a minimal number of photolithographic masking steps and being fail-safe in a number of respects. A number of process alternatives are disclosed for forming a shorting extension of a base region up through and to a portion of the surface of a source region, many of these process alternatives involving self-masking techniques to define the source region surface portion. Two general MOSFET structures are formed in accordance with the procedures of the invention. One structure has metallized gate terminal fingers, and is formed employing one-mask processes. The other structure has gate fingers encased in insulating oxide and connected to remote gate contacts. For both structures, selective oxidation of the polysilicon gate electrode material is preferred, and various approaches to this selective oxidation are described.

REFERENCES:
patent: 4084986 (1978-04-01), Aoki et al.
patent: 4148054 (1979-04-01), Hart et al.
patent: 4232439 (1980-11-01), Shibata
patent: 4242791 (1981-01-01), Horng et al.
patent: 4290844 (1981-09-01), Rotolante et al.
patent: 4319395 (1982-03-01), Lund et al.
patent: 4344081 (1982-08-01), Pao et al.
patent: 4345265 (1982-08-01), Blanchard
Leung et al., "Refractory Metal Silicide/N+Polysilicon in CMOS/SOS," Technical Digest of International Electron Devices Meeting, Washington D.C., Dec. 8, 1980, Institute of Electrical and Electronics Engineers, Piscataway, N.J., pp. 827-830.
J. F. Gibbons, "Ion Implantation in Semiconductors--Part I: Range Distribution Theory and Experiments", Proceedings IEEE, vol. 56, No. 3, pp. 295-319 (Mar. 1968).
J. F. Gibbons, "Ion Implantation in Semiconductors--Part II: Damage Production and Annealing", Proceedings IEEE, vol. 60, No. 9, pp. 1062-1096 (Sep. 1972).
J. Hui, T. Y. Chiu, S. Wong, and W. G. Oldham, "Selective Oxidation Technologies for High Density MOS", IEEE Electron Device Letters, vol. EDL-2, No. 10, pp. 244-247 (Oct. 1981).
Specification & drawings of copending U.S. patent application Ser. No. 324,328, filed 11-23-81, by B. J. Baliga, "Methods for Fabricating Vertical Channel Buried Grid Field Controlled Devices Including Field Effect Transistors and Field Controlled Thyristors".
Specification & Drawings of copending U.S. patent application Ser. No. 324,163, filed 11-23-81, by B. J. Baliga et al., "Vertical Channel Field Controlled Device Employing a Recessed Gate Structure and Methods of Making".
Specification & drawings of copending U.S. patent application Ser. No. 336,972, filed 1-4-82 by R. P. Love, "Self-Aligned Power MOSFET with Integral Source-Base Short and Methods of Making".

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