Process window compliant corrections of design layout

Details Process window compliant corrections of design layout Process window compliant corrections of design layout

2007-12-25

2007-12-25

Frejd, Russell (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C700S121000, C716S030000, C716S030000, C430S005000, C430S030000

Reexamination Certificate

active

10330929

ABSTRACT:
The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.

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