Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2001-12-21
2004-03-30
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257SE21268, C257SE21293, C257SE21546, C257SE21550
Reexamination Certificate
active
06713780
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor device manufacturing, and in particular to a method of fabricating a trench isolation region, such as a shallow trench isolation (STI) region, within a substrate, wherein the trench isolation region is substantially planar and contains trench isolation/substrate corners that are rounded. By forming rounded corners, the present invention substantially eliminates the formation of divots at the trench isolation/substrate corner. The method of the present invention thus prevents polysilicon rail formation and reduces the early turn-on characteristics of transistors.
BACKGROUND OF THE INVENTION
In the manufacturing of semiconductor devices, it is well known to form isolation regions that electrically isolate the various active regions present within the device from each other. One method of electrically isolating the active device regions is to form a trench isolation region between adjacent devices. Such prior art trench isolation regions typically comprise a trench that is formed within the substrate and filled with a dielectric material such as SiO
2
.
Three categories of trench isolation regions are known: including shallow trenches (trenches whose depth is less than about 1 &mgr;m), moderate trenches (trenches whose depth is from about 1 to about 3 &mgr;m), and deep trenches (trenches whose depth is greater than 3 &mgr;m). As the size of the semiconductor devices is continuously being scaled down, there is a greater interest in employing STI (shallow trench isolation) regions.
The prior art describes many different techniques that can be used in forming the STI regions within a substrate. One such prior art technique is shown in
FIGS. 1A-1E
. Specifically,
FIG. 1A
illustrates a fragment of wafer
10
that contains a semiconducting substrate
12
such as Si, upon which is formed an oxide layer
14
, a nitride layer
16
and a patterned photoresist
18
. Such a structure is formed utilizing conventional deposition steps and the patterned photoresist is formed by conventional lithography, e.g., applying a photoresist; exposing the photoresist to radiation so as to form a pattern in said photoresist and developing the pattern.
Referring to
FIG. 1B
, patterned photoresist
18
is used as a mask during a subsequent etching process. Thus during etching, unmasked portions of nitride layer
16
, oxide layer
14
and semiconducting substrate
12
are removed using a dry etch process, i.e., reactive-ion etching (RIE), to form trench
20
within the substrate.
Next, as shown in
FIG. 1C
, the patterned photoresist is removed utilizing a conventional stripping process, and thereafter an oxide layer (or other trench dielectric material)
24
is deposited over the nitride layer and within the trench. Following the trench fill, oxide layer
24
is planarized down to upper surface
17
of nitride layer
16
by utilizing a conventional planarization process such as chemical-mechanical polishing (CMP) or grinding, See FIG.
1
D. The planarization process forms an oxide plug
26
within the trench. As is also shown in
FIG. 1D
, oxide plug
26
has an upper surface
28
substantially co-extensive with upper surface
17
. The plug also comprises sidewalls
33
and upper corners
34
where the sidewalls join upper surface
28
.
Ideally, the upper surface of the plug would be planar, i.e., comprise a flat surface. Also, ideally, the corners of the plug comprise a 90° angle, and would therefore be substantially square. However, due to the practical limitations of the planarization process used, these ideal objectives cannot be met. Instead, as shown in
FIG. 1D
, surface
28
is concave instead of flat and the corners of the isolation region are not square.
In some cases, portions of plug
26
are removed at the corners of the STI region causing the formation of divots
30
, See FIG.
1
E. These divots would exist at the corner of the STI even if layers
14
and
16
are removed. The presence of divots at the STI/substrate corner is undesirable since they create unwanted features, such as polysilicon rails and an early turn-on characteristic in the device. In view of these drawbacks, methods are continuously being sought to eliminate the divots at the STI/substrate corner.
To date however no method has been developed that can provide a planar STI region that contains no divots at the corner regions between the STI and the substrate. The development of a method that is capable of fabricating a planar STI region containing no divots at the corners of the STI regions would represent a significant advancement in the art since it would improve the corner threshold voltage control of the structure making the structure suitable for use in a wide variety of logic and memory applications. Moreover, such a method would be beneficial since it would substantially eliminate the presence of polysilicon rails as well as reduce the early turn-on characteristics of the device.
SUMMARY OF THE INVENTION
The present invention provides a method of fabricating a semiconductor structure in which a substantially planar trench isolation region containing rounded trench isolation/substrate corners is formed—the rounded corners are advantageous in the present invention since they phase out divot formation—. Since the trench isolation regions of the present invention contain rounded corners, polysilicon rails and other like unwanted features are eliminated. The term “trench” includes deep trenches, moderate trenches and shallow trenches, whereas the term “trench isolation region” includes shallow trench isolation regions, moderate trench isolation regions and deep trench isolation regions.
Specifically, the method of the present invention comprises the steps of:
(a) forming a film stack on a surface of a substrate, said film stack comprising an oxide layer, a polysilicon layer and a nitride layer;
(b) patterning said film stack so as to form at least one trench within said substrate, wherein said patterning exposes sidewalls of said oxide layer, polysilicon layer and nitride layer;
(c) oxidizing the at least one trench and said exposed sidewalls of said oxide layer and said polysilicon layer so as to thermally grow a conformal oxide layer in said trench and on said exposed sidewalls of said oxide layer and said polysilicon layer;
(d) filling said trench with a trench dielectric material; and
(e) planarizing to said surface of said substrate.
The present invention also provides semiconductor devices which include at least one substantially planarized trench isolation region within a substrate, said planarized trench isolation region containing rounded corners which substantially phase away the formation of divots at the trench isolation/substrate corners.
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patent: 5177028 (1993-01-01), Manning
patent: 5731241 (1998-03-01), Jang et al.
patent: 5741738 (1998-04-01), Mandelman et al.
patent: 5786262 (1998-07-01), Jang et al.
patent: 5834358 (1998-11-01), Pan et al.
patent: 5970362 (1999-10-01), Lyons et al.
patent: 6027982 (2000-02-01), Peidous et al.
patent: 6153472 (2000-11-01), Ding et al.
patent: 6251746 (2001-06-01), Hong et al.
patent: 3-94094 (1991-04-01), None
patent: 100 72694 (1998-03-01), None
International Business Machines - Corporation
Niebling John F.
Pompey Ron E.
Sabo, Esq. William D.
Scully Scott Murphy & Presser
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