Process-tolerant integrated circuit design

Details Process-tolerant integrated circuit design Process-tolerant integrated circuit design

1999-03-08

2002-12-17

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S538000, C327S541000

Reexamination Certificate

active

06496056

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to process-tolerant design techniques for use in complementary metal-oxide-semiconductor (CMOS) integrated circuits or other types of electronic circuits.
BACKGROUND OF THE INVENTION
Process variations are an important consideration in the design of many different types of integrated circuits.
FIG. 1
shows a portion of a CMOS integrated circuit
10
which serves to illustrate the impact of process variations on circuit performance. The circuit
10
includes a phase-locked loop (PLL)
12
, a voltage-controlled oscillator (VCO)
14
, and a voltage regulator circuit
16
. The voltage regulator circuit
16
generates a regulated output voltage from a generally variable supply voltage V
DD
. The variation in the supply voltage V
DD
is often on the order of ±20% of its nominal value.
The regulated voltage is supplied to the VCO
14
and thereby to the PLL
12
. The PLL
12
receives an input stream and generates a control voltage which adjusts the frequency of the VCO output such that the PLL output is phase-locked with the input stream. The circuit
10
is often required to operate at frequencies at or above the GHz range, and must meet specified performance criteria in the presence of variation in the supply voltage V
DD
, e.g., a ±20% variation. In addition, the circuit
10
must meet the specified performance criteria in the presence of variations in the CMOS wafer processes used to construct the circuit.
In the circuit
10
, the voltage regulator circuit
16
serves to remove the variation in the supply voltage V
DD
, and the effects of the process variations are dealt with using the negative feedback loop between the PLL
12
and the VCO
14
. The output of the voltage regulator circuit
16
is in the form of a constant voltage independent of any variation in the supply voltage V
DD
, and may be generated using a so-called bandgap voltage reference circuit. In order to provide sufficient margin to accommodate the specified variation in V
DD
, the regulator output voltage is generally made somewhat lower than the expected minimum V
DD
value, typically about V
BE
≈600 millivolts or more lower than the expected minimum V
DD
value. As the V
DD
value is reduced, e.g., from 5 volts to 3.3 volts to 2.5 volts depending on the circuit implementation and CMOS process used, it becomes increasingly difficult to provide the desired amount of voltage margin.
With regard to the process variations, the control voltage from the PLL
12
to the VCO
14
in circuit
10
will generally vary depending on these variations, even if the operating frequency of the circuit remains unchanged. For example, if an N-channel field effect transistor (NFET) controls the VCO delay, the control voltage to the VCO will be higher if the process shifts to its slower side. This type of variation further narrows the design margin.
Conventional integrated circuit design techniques, such as those used to address supply voltage variations and process variations in the circuit
10
of
FIG. 1
, are insufficiently tolerant to these types of variations, particularly as V
DD
is reduced, e.g., below 3.3 volts. Moreover, such techniques are generally unable to make time-varying circuit operating parameters substantially independent of process variations. A need therefore exists for improved integrated circuit design techniques.
SUMMARY OF THE INVENTION
The invention makes an operating parameter of an integrated circuit substantially insensitive to process variations by configuring the circuit such that an environmental parameter which affects the opeating parameter is made a function of one or more process parameters. In this manner, the effect of the process parameters on the circuitoperating parameter may be partially orsubstantially offset by the effect of the process parameters on the environmental parameter. Examples of environmental parameters which may be used in this compensation technique include power supply voltage, current generator control voltages, active load control voltage, back-bias voltage, and operating temperature. Examples of.process parameters suitable for use in this,compensation technique include conduction ethreshold voltage, channel nobility, gate capacitance, drain capacitance, Early voltage, saturation parameter, transit time and other parameters associated with the field effect transistors (FETs) of the integrated circuit.
In an illustrative embodiment, the circuit operating parameter is an oscillation period of a ring oscillator. A voltage regulator generates a reference voltage which is determined at least in part based on known process parameter variations in the ring oscillator. The ring oscillator utilizes the reference voltage generated by the voltage regulator as its power supply voltage, and its oscillation period is thereby made insensitive to the process parameter variations. In addition, back-bias effects may be introduced in the voltage regulator to compensate back-bias effects resulting from particular configurations of the ring oscillator.
The design techniques of the invention may be applied to a wide variety of different types of circuits, operating parameters, environmental parameters and process parameters. In addition, the invention allows a circuit operating parameter which varies as a function of time, such as the above-noted oscillation period, to be made substantially process independent. The invention can be applied, e.g., to produce fixed operation frequency integrated circuits at high yield, and to achieve specified performance at low power supply voltages, e.g., on the order of 2 volts or less. The process variation tolerant design techniques of the present invention are particularly well-suited for use in high-speed CMOS integrated circuit applications, although as previously noted the invention is also suitable for use with other types of circuits. These and other advantages and features of the present invention will become more apparent from the accompanying drawings and the following detailed description.


REFERENCES:
patent: 3970875 (1976-07-01), Leehan
patent: 5359302 (1994-10-01), Balusek
patent: 5831472 (1998-11-01), Wang et al.
M. Shoji, “Elimination of Process-Dependent Clock Skew in CMOS VLSI,” IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, pp. 875-880, Oct. 1986.

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