Process to reduce surface roughness of low K damascene

Details Process to reduce surface roughness of low K damascene Process to reduce surface roughness of low K damascene

2001-09-27

2003-09-09

Powell, William A. (Department: 1765)

Etching a substrate: processes

Planarizing a nonplanar surface

C216S088000, C438S692000, C438S745000

Reexamination Certificate

active

06616855

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of damascene structures in micro-circuits with particular reference to their formation inside porous layers.
BACKGROUND OF THE INVENTION
The continued reduction in the dimensions of all parts of microcircuits includes the wiring channels and vias. Additionally, improvements in performance have been effected by the introduction of copper wiring and low K dielectrics. Among the most successful of the latter has been porous silica wherein the presence of uniformly distributed micro-bubbles allows the dielectric constant to be reduced to values as low as 2.5 or less. For the implementation of copper wiring, dual damascene structures have been widely adopted.
In
FIG. 1
we show a schematic representation of a cross-section of a damascene structure. Dielectric layer
12
has been laid down over wiring level
11
. Extending downwards from trench
15
(which will serve as a wiring channel at the next level) is via hole
14
. When the structure has been filled with copper, via
14
provides a connection between the two wiring levels. Because of its high diffusivity and its proclivity for acting as a recombination center in silicon, steps must be taken to ensure that all the copper is confined to the damascene structure. This is routinely accomplished by the inclusion of a barrier layer (not shown) that lines the walls of the trench and the via hole.
As the porosity of porous silica is increased (with a corresponding decrease in the dielectric constant) there is a growing tendency for surfaces of porous silica that have been etched to exhibit significant roughness. Where the surface in question is the floor of a trench, (such as
15
in FIG.
1
), the result is as marked schematically as surface
21
in FIG.
1
. This, in turn, means that a much thicker barrier layer than normal is needed to be sure that there are no thin patches through which copper could move. In the absence of the afore-mentioned roughness problem, a barrier layer about 300 Angstroms thick is sufficient to contain the copper whereas, in the presence of a rough trench surface, this has to be increased to at least 500 Angstroms.
FIG. 2
illustrates one solution to this problem that has been used by the prior art. As part of the trench formation process, an etch stop layer
13
is included. This means that the degree of roughness on the trench's floor will be determined by the etch stop layer and not by the porous silica. Typically, layer
13
is about 300-500 Angstroms thick and, as already noted, the barrier layer is about 300 Angstroms thick. For a trench depth of about 0.3 microns, that leaves only about 2,200-2,400 Angstroms for copper which is less than would be preferred since the trench width is only about 1,600 Angstroms. Additionally, the thicker stop layer will increase the overall line-to-line capacitance.
Roughening of the trench and via sidewalls is not a problem because the sidewall is not directly bombarded by the etching species, so a preferred solution would be to find a way to reduce or eliminate the roughness at the trench floor, thereby allowing a thinner barrier layer to be used.
A routine search of the prior art was performed with the following references of interest being found:
In U.S. Pat. No. 6,235,628, Wang et al. disclose a dual damascene process with a middle etch stop layer. In U.S. Pat. No. 5,621,197, Yu shows a SOG sacrificial layer process. U.S. Pat. No. 6,211,0.61 (Chen et al.) reveals a dual damascene process with no middle etch stop layer while in U.S. Pat. No. 6,184,128, Wang also shows a dual damascene process. U.S. Pat. No. 6,110,648 (Jang), U.S. Pat. No. 5,731,241(Jang et al.), and U.S. Pat. No. 6,057,239 (Wang et al.) are all related dual damascene patents.
SUMMARY OF THE INVENTION
It has been an object of at least one embodiment of the present invention to provide a process for etching a trench in a layer.
Another object of at least one embodiment of the present invention has been that said process result in a trench whose floor has a lower roughness value than a similar trench produced using prior art processes.
Still another object of at least one embodiment of the present invention has been that said process be readily incorporable into processes for forming dual damascene structures.
A further object of at least one embodiment of the present invention has been that said process not require the presence of an etch stop layer during trench formation.
These objects have been achieved by fully covering the trench floor with a layer of a flowable material. Then an etchant is provided that etches both the trench and flowable materials at approximately the same rate, Using this etchant, the trench floor is then uniformly etched until only a small amount of flowable material remains. After any and all remaining flowable material has been removed, it is found that the roughness at the trench floor has been reduced by a factor of about 3-5. This allows a barrier layer of normal thickness to be used during the standard copper damascene process without danger of copper leakage. The process is particularly well suited for use with porous silica dielectrics having a dielectric constant less than about 2.5.


REFERENCES:
patent: 5631197 (1997-05-01), Yu et al.
patent: 5731241 (1998-03-01), Jang et al.
patent: 6057239 (2000-05-01), Wang et al.
patent: 6110648 (2000-08-01), Jang
patent: 6184128 (2001-02-01), Wang et al.
patent: 6211061 (2001-04-01), Chen et al.
patent: 6235628 (2001-05-01), Wang et al.
patent: 6242356 (2001-06-01), Jang et al.

Affiliated with

Also associated with

Rating

Process to reduce surface roughness of low K damascene does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process to reduce surface roughness of low K damascene, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process to reduce surface roughness of low K damascene will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3050959