Coating processes – Direct application of electrical – magnetic – wave – or... – Ion plating or implantation
Reexamination Certificate
1998-07-22
2001-10-16
Pianalto, Bernard (Department: 1762)
Coating processes
Direct application of electrical, magnetic, wave, or...
Ion plating or implantation
C427S099300, C427S103000, C427S255270, C427S255700, C427S407100, C427S529000, C427S530000, C427S531000, C427S535000, C427S539000, C427S579000, C427S585000, C427S590000
Reexamination Certificate
active
06303192
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor manufacturing processes, and more particularly to techniques for improving the adhesion of plasma enhanced chemical vapor deposition (PECVD) cap layer to an underlayer that includes methyl compounds.
2. Description of the Related Art
As semiconductor manufacturing technology produces devices that are faster and more efficient, both the density of conductive lines and the frequency of charges flowing on the conductive lines tend to increase. Because semiconductors rely on insulating (i.e. dielectric) layers to reduce capacitive coupling between the conductive lines, it has become increasingly important to have insulation that is able to accommodate both the higher operating frequencies and the shrinking distances between the lines.
FIG. 1A
is a cross-sectional view illustrating the respective layers of a typical semiconductor structure
10
. The semiconductor structure
10
is made up of several layers including a PECVD cap layer
12
, a spin on glass (SOG) layer
14
that is preferably made from a silicate base, and a semiconductor substrate
16
. The semiconductor substrate
16
typically supports a first metal layer
18
formed into a number of conductive traces
18
a,
18
b,
18
c
and
18
d.
A second metal layer
22
including traces
22
a
and
22
b
may be provided over the PECVD cap layer
12
. A number of conductive vias, such as conductive via
20
, are provided through the SOG layer
14
and the PECVD cap layer
12
, connecting the traces of metal layer
18
to traces of metal layer
22
. For ease of illustration, only one conductive via
20
and six metal traces
18
a-d
and
22
a-b
are shown, but as is well known in the art, many more conductive vias and metal traces are used to provide appropriate connections in a semiconductor or integrated circuit device.
A first plurality of capacitive couplings
26
exist between the first metal layer
18
and the second metal layer
22
. A second plurality of capacitive couplings
28
exist between the metal traces
18
a-d.
The purpose of the SOG layer
14
is to insulate the metal traces and to reduce capacitive couplings
26
and
28
by providing a dielectric between the traces.
With higher line density and higher operating frequencies, the coupling capacitances
26
and
28
are increasing to the point that SOG layer
14
is a less than adequate insulator. Raising the operating frequency requires a reduction in both the first coupling capacitance
26
and the second coupling capacitance
28
. However, increasing the densities of the metal traces
18
a-d
decreases the distance d
1
between each of the metal traces
18
a-d
which increases the second capacitive coupling
28
.
Another important dimension in
FIG. 1A
is the thickness t
1
of the SOG layer
14
. If the insulating material can be made thicker, the first coupling capacitance
26
can be reduced. Unfortunately, the SOG layer
14
may have only a maximum thickness t
1
of about 3,000 Angstroms. If the SOG layer thickness t
1
exceeds 3,000 Angstroms, the SOG layer
14
will begin to crack and form rifts
30
. Therefore, semiconductors need an alternative material that is both a better insulator (having a lower dielectric constant) and which resists cracking.
One way for improving silicate SOG material is to add methyl (—CH
3
) groups as side groups to the silicate backbone. Such a material is referred to as methyl silsesquioxane (MSQ) based SOG. Adding methyl side groups lowers the dielectric constant of the SOG insulating layer and allows a thickness greater than 3,000 Angstroms of the SOG layer without cracking. Unfortunately, adding methyl side groups to SOG also causes the PECVD cap layer, which is added to protect the semiconductor structure, to peel away during a subsequent chemical mechanical polishing (CMP) process used to planarize the cap layer. This is because the cap layer doesn't adhere well to the MSQ-SOG layer.
FIG. 1B
is a cross-sectional view illustrating the respective layers of a semiconductor structure
32
incorporating an MSQ-SOG layer
34
. When a methyl compound (e.g. MSQ) is added to the SOG, it lowers the relative dielectric constant of the insulating layer from about 4.0 to about 2.8. In addition, an MSQ-SOG layer
34
can have a thickness t
2
of up to about 5,000 Angstroms without cracking. However, the PECVD cap layer
12
does not adhere well to the MSQ-SOG layer
34
and tends to peel and flake away from the MSQ-SOG layer
34
during subsequent CMP processes, as noted previously.
One method of improving adhesion between the MSQ-SOG layer
34
and the PECVD cap layer
12
is to use a reactive ion etching (RIE) tool to bombard the MSQ-SOG layer
34
with an oxygen (O
2
) plasma. However, a problem with using the RIE-O
2
technique is that the semiconductor wafer must be moved to an RIE tool, be processed in the RIE tool, and then returned to the PECVD tool. This adds a great deal of time and cost to the process.
FIG. 1C
shows a flow chart of a prior art solution to reduce PECVD cap layer peeling. In an operation
36
, a metal layer is deposited to begin the forming of an integrated circuit. In an operation
38
, a MSQ-SOG layer is deposited on top of the metal layer. In operation
40
, the methyl layer SOG is surface treated by using an reactive ion etching tool with oxygen plasma (RIE-O
2
) to convert a thin surface portion (“skin”) of the MSQ-SOG layer into SiO
2
.
Moving the unfinished wafer to a RIE-O
2
tool, and then transferring the wafer back to the original processing chamber to deposit the cap layer necessarily adds substantial cost and time to the process. In addition, wafers are often processed in batches, causing even more delay at the RIE tool. Finally, in operation
42
, the PECVD cap oxide is deposited, adhering to the SiO
2
skin.
In view of the foregoing, it is desirable to have a method that provides for a low dielectric constant, low-cracking insulating material that adheres well to the PECVD cap layer without adding significant time or cost to the process.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing an efficient and economical method for improving adhesion of MSQ-SOG material and PECVD cap oxide. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for making a multi-layered integrated circuit structure is disclosed. This method includes: (a) depositing a methyl compound spin on glass layer over a substrate; and (b) plasma-deposition treating the spin on glass layer under a first set of conditions to form an SiO
2
skin on the SOG layer and then under a second set of conditions to form a cap layer which adheres to the SiO
2
skin. Preferably, the plasma-depositions are performed in a same processing chamber.
An advantage of the present invention is that it improves adhesion between MSQ-SOG and PECVD cap oxide. MSQ-SOG is a vast improvement over standard SOG because it has a lower dielectric constant. Furthermore, MSQ-SOG material can also be made much thicker than normal SOG because it resists cracking. Both of these factors reduce inter metal capacitance in the integrated circuit.
An additional advantage of the present invention is that it improves the adhesion of the MSQ-SOG and the PECVD cap layer without the additional procedures, time and expense associated with using a separate RIE-O
2
tool. Instead, the oxygen ion bombardment can be accomplished using the same PECVD tool that is necessary to deposit the cap layer in a matter of seconds. Therefore, the process of the present invention saves time and money, as well as reduces the chance for contamination of the semiconductor wafer during the transfer of the wafer.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in
Annapragada Rao V.
Bothra Subhas
Tafari Tekle M.
Oppenheimer Wolff & Donnelly LLP
Philips Semiconductor Inc.
Pianalto Bernard
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