Process-, temperature-, and voltage-compensation for ECL delay c

Oscillators – Ring oscillators

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Details

307602, 307603, 307605, 307608, 307304, H03K 3354, H03K 514

Patent

active

053593014

ABSTRACT:
Low-cost apparatus and method for achieving a moderately-precise resistance value into an integrated circuit without the use of resistive trimming or complex feedback loops. The invention has direct application to the production of integrated BiCMOS circuits making use of Delay Lines and/or Voltage-Controlled Ring Oscillators where a .+-.10% tolerance in delay time or frequency is acceptable. When incorporated into a PLL, it also presents advantages where tighter tolerances are required, because of its low inherent jitter. By the use of a single off-chip component, this invention overcomes variations in the operating circuit otherwise arising from chip fabrication irregularities, power supply voltage fluctuations, and ambient temperature drift. In the Preferred Embodiment of the present invention, the resistive element is used as the load resistor of a high-frequency ECL delay cell; the element is a controlled MOSFET resistor in parallel with a fixed diffusion resistor. This parallel resistor is made into a compensated calibrated resistor by coupling it into a current mirroring circuit and an external resistor of a precise value. In its Preferred Embodiment, the invention combines the mirroring of current and resistance into a delay cell with the use of an oxide capacitor (a MOSCAP) as the capacitive part of the delay cell's RC time constant and in so doing achieves a delay cell with a delay time which is predictable to within .+-.10% without the use of any complex feedback loops, such as occur in a Phase-Locked Loop.

REFERENCES:
patent: 4810907 (1989-03-01), Tohyama
patent: 4864162 (1989-09-01), Maoz
patent: 4988960 (1991-01-01), Tomisawa
patent: 5010385 (1991-04-01), Shoemaker

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