Process, supply, temperature compensating CMOS output buffer

Details Process, supply, temperature compensating CMOS output buffer Process, supply, temperature compensating CMOS output buffer

1989-11-09

1991-06-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307473, 307263, 307546, 3072968, H03K 1716

Patent

active

050216848

ABSTRACT:
A design for a high performance CMOS output buffers utilizing a process, supply and temperature conpensated current source to achieve very tight distribution of rise/fall times and propagation delays. The output buffer has been optimized to limit switching noise by using current controlled predrivers. An output buffer according to the present invention can switch up to a 100 pf load to TTL levels with rise times of no more than 4.0 ns and propagation delays ranging from 2.1 ns to 11.6 ns over the entire range of process, supply, temperature, and load for a typical one micron CMOS process; Vcc from 4.5 to 5,5V, temperature from -10 to 120.degree. C., and loads from 10 to 100 pf.

REFERENCES:
patent: 4638187 (1987-01-01), Boler et al.
patent: 4725982 (1988-02-01), Hara et al.
patent: 4760292 (1988-07-01), Bach
patent: 4857770 (1989-08-01), Pantovi et al.
patent: 4928023 (1990-05-01), marshall

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