Process request arbitration system which preferentially maintain

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Details

3642592, 3642426, 3642427, 364240, 364DIG1, G06F 1336

Patent

active

051931966

ABSTRACT:
A plurality of process requests generated from processing units, for example, direct memory access (DMA) channels are controlled by a preference circuit in accordance with a priority level assigned to each of the processing unit. An information of the highest priority obtained processing unit and its priority level is stored in latches. Another process requests having the same priority level as the stored processing unit are inhibited from being supplied to the preference circuit, so that the first generated process request is accepted and executed prior to acceptance of the another process requests having the same priority level.

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