Process or renders repeat operation instructions non-cacheable

Details Process or renders repeat operation instructions non-cacheable Process or renders repeat operation instructions non-cacheable

1995-12-13

1998-04-28

Swann, Tod R.

Boots, shoes, and leggings

395445, 395403, 395375, 364DIG1, G06F 1208

Patent

active

057457280

ABSTRACT:
A Central Processing Unit is provided having an instruction processor for determining CPU instruction types. An instruction detector is included in the CPU for detecting whether a determined instruction is a non-cacheable repeat operation instruction. The CPU has an execution unit for executing instruction and for outputting a CPU signal indicating whether data associated with an instruction is cacheable.

REFERENCES:
patent: 4437149 (1984-03-01), Pomerene
patent: 5058006 (1991-10-01), Durdan et al.
patent: 5226138 (1993-07-01), Shermis
patent: 5301295 (1994-04-01), Leary et al.
patent: 5333296 (1994-07-01), Bouchard et al.
patent: 5481689 (1996-01-01), Stamm et al.

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