Process of thinning and blunting semiconductor wafer edge...

Details Process of thinning and blunting semiconductor wafer edge... Process of thinning and blunting semiconductor wafer edge...

2000-09-29

2002-10-15

Fourson, George (Department: 2623)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S977000

Reexamination Certificate

active

06465353

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor wafer structure and process for its manufacture and more specifically relates to an ultra thin wafer and process for blunting the outer peripheral edge of a wafer.
BACKGROUND OF THE INVENTION
Semiconductor wafers such as thin monocrystaline silicon wafers are commonly used in semiconductor device fabrication. These wafers can have any desired diameter, for example, 1″ to 10″ and have varying thicknesses, typically about 300 to 600 microns. The entire wafer is photolithographically processed, receiving on its top surface a large number of spaced sets of diffusions, oxidations, etches, washes, metal layers and the like to form a large number of identical devices such as transistors, diodes, and other such devices. After processing, the wafers are frequently thinned by grinding from the wafer back surface to a thickness desired to satisfy a desired characteristic of the device. The individual devices are then separated by cutting through the wafer.
It is well known to generally round the edge of the wafer before processing to prevent chipping and cracking of the thin, brittle monocrystaline wafer during processing. However, when wafers with this prior rounding process are reduced in thickness to less than about 100 microns, the resulting tapered edge is razor sharp and becomes dangerous to handle in the wafer fabrication facility. Further, the razor sharp edge will easily cut into or catch into surfaces within the fabrication facility and crack or impede the desired movement of the wafer between different process step positions.
Many recent semiconductor devices have a need for ultrathin semiconductor die. For example, Insulated Gate Bipolar Transistors of the “punch-through” type and with a “transparent” collector region and rated at 600 volts or more can be made in wafers about 100 microns thick. Other voltage ratings require even thinner wafers, some as thin as 70 microns. Such devices are described in co-pending application Ser. No. 09/565,973, filed May 5, 2000 (IR 1707). These wafers are initially about 400 microns thick and are sufficiently strong to resist breakage during the processing of the top surface of the wafer. The wafers, with conventionally rounded edges are then ground from one side, for example, to a thickness of less than about 100 microns, and the ground surface is then exposed to a stress relief treatment. Top metal is then added and the wafers are diced. If the back grind is greater than one half of the initial wafer thickness, the back surface will meet the rounded edge with an acute angle, forming a razor-like edge. The extremely sharp tapered edge of the 100 micron thick wafer (or even less) can easily cut personnel and can cut into the processing equipment as the wafers are moved to different positions and are loaded or unloaded from wafer boats.
BRIEF DESCRIPTION OF THE INVENTION
In accordance with the invention, the outer edge of a wafer after thinning is squared or otherwise blunted to remove its tapered razor edge. This blunting operation may be performed as by grinding after a front metal is applied, but may be performed at any step of the process after the wafer is thinned. The resulting wafer then has a blunted cutting edge and is less dangerous to handle and is less likely to be hung up in the processing equipment. Further, the material removed by grinding is tapered and is unsuitable to contain useful die, so that useful silicon area is not sacrificed.


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patent: 6337257 (2002-01-01), Toyosawa
patent: 2001/0015168 (2001-08-01), Dietze et al.

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