Process of testing memory parts and equipment for conducting the

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G11C 2900

Patent

active

058621466

ABSTRACT:
A process and apparatus for testing wide word memory parts (618-624), sixteen data I/O leads per part, uses two stages of relays (610, 612 and 614) to connect the memory parts to sixteen test receivers (Ra, Rb, Rc and Rd). When the memory parts are in a normal operating mode or non-DFT mode, the relays connect all sixteen data I/O leads of each memory part to the sixteen test receivers, one memory part at a time. When the memory parts are in the DFT mode, the relays connect all the active DFT data I/O leads (0-3) to the receivers. A test performance board can carry one or more modules of memory parts with each module containing plural sockets for retaining the memory parts and one or more stages of relays.

REFERENCES:
patent: 4686456 (1987-08-01), Furuyama et al.
patent: 5365165 (1994-11-01), El-Ayat et al.
patent: 5579272 (1996-11-01), Uchida
patent: 5717643 (1998-02-01), Iwanami et al.

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