Process of plating selective areas on a printed circuit board

Details Process of plating selective areas on a printed circuit board Process of plating selective areas on a printed circuit board

1998-07-20

2000-02-08

Gorgos, Kathryn

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Coating selected area

205125, 205920, C25D 502

Patent

active

060224665

ABSTRACT:
A process for plating gold on a multi-layered printed circuit board, having plated copper on an external surface. In one embodiment, first copper features for plating gold thereon and second copper features for plating copper thereon are selected on the external surface. The first copper features are internally connected to the second copper features. An etch-resist on the first and second copper features is deposited. The second copper features are masked, while a region containing the first copper features is exposed. Copper from the region is etched. The etch-resist on the first copper features is removed. Gold is then plated on the first copper features.

REFERENCES:
patent: 4024631 (1977-05-01), Castillero
patent: 4325780 (1982-04-01), Schultz, Sr.
patent: 4394223 (1983-07-01), Hall
patent: 4444619 (1984-04-01), O'Hara
patent: 5169692 (1992-12-01), Couble et al.
patent: 5733466 (1998-03-01), Benebo et al.
patent: 5747098 (1998-05-01), Larson

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