Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Passivating of surface
Reexamination Certificate
2002-03-15
2004-08-03
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Passivating of surface
C438S199000, C438S528000, C438S565000
Reexamination Certificate
active
06770500
ABSTRACT:
BACKGROUND OF THE DISCLOSURE
1. Field of the Invention
The present invention is directed to a process of passivating a metal-gated complementary metal oxide semiconductor (CMOS) by lowering the interface state density between the silicon substrate and the dielectric of the metal-gated CMOS structure and reducing the fixed charge in the dielectric. More preferably, the present invention is directed to a process of passivating a metal-gated CMOS by exposing that CMOS to an atmosphere of molecular hydrogen at an elevated temperature higher than room temperature.
2. Background of the Prior Art
Passivation of CMOS structures, in the prior art, when polysilicon-gated CMOS structures were predominant, was typically conducted by exposing the CMOS structure to forming gas (FG) annealing. Such passivation resulted in a density of interface states (Dit) less than 5e10/cm
2
-eV. Although passivation of polysilicon-gated CMOS structures is presently successfully practiced using FG annealing, this method has been demonstrated to be inadequate when the CMOS structure is a metal-gated CMOS, specifically when tungsten is the metal gate.
Metal-gated CMOS structures have not yet been fully commercialized and are still in the exploratory phase. However, metal-gated structures are expected to be utilized in the future. Thus, there is a strong need in the art for an effective process of passivation of metal-gated CMOS structures. Those skilled in the art are aware that metal-gated CMOS structures may employ a single mid-gap metal, e.g., tungsten, or a dual metal option with a suitable nfet metal, such as aluminum, titanium, tantalum nitride or alloys thereof, or a pfet metal, e.g. rhenium or rhodium.
FG annealing of CMOS structures performed after deposition of tungsten metal at temperatures between 350 to 550° C. does not result in a low enough Dit. Insofar as passivation of the dielectric/silicon interface by FG anneals occurs prior to tungsten metal deposition, depassivation of the CMOS structure occurs during deposition. In addition, passivation by FG annealing may result in an increase in dielectric thickness, due to the formation of interfacial silica. Insofar as thickness of the CMOS structure is critical to conform with scaling targets, this thickness increase of up to about five angstroms evidences yet another reason for the need of a new process for the passivation of metal-gated CMOS structures.
The above remarks are supported by quantitative data. The prior art anneal passivation technique of FG annealing produces Dit values for a typical metal-gated CMOS structure in which the gate dielectric is silica and the gate conductor is tungsten of more than 1e11/cm
2
-eV. This Dit is much too high for effective use of the CMOS. There is also some evidence that some of the gate metals currently being contemplated for use in metal-gated CMOS structures specifically for the dual metal option, are thermally unstable beyond 500° C., thus necessitating a low temperature post-metal passivation process.
A recent passivation process has been developed for metal-gated CMOS structure. That process, utilized in a tungsten-gated silica structure, is disclosed in a commonly assigned U.S. patent application Ser. No. 09/760,621, filed Jan. 16, 2001, which produces Dit's in the range of about 3e10/cm
2
-eV. This passivation process employs hydrogen plasma.
Hydrogen plasma is employed because it results in the formation of atomic hydrogen which passivates the dielectric/silicon interface. However, the presence of a plasma complicates the process by making it expensive and ill well suited to batch processing. In addition, hydrogen plasma may have a detrimental effect upon the gate electrode or other parts of the CMOS structure. That is, the plasma may damage the gate electrode or other parts of the CMOS structure due to the production of reactive atomic hydrogen. Thus, the copending application, although representing a very significant advance in the art, still does not fully solve the problems associated with passivation of metal-gated CMOS structures.
The above remarks suggest the criteria necessary for a successful passivation process for newly developed metal-gated CMOS structures. First, the passivation process must result in a Dit of less than about 5e10/cm
2
-eV at the dielectric/silicon interface. Second, the passivation technique must be performed at a relatively low temperature, specifically <400° C. Third, the process should tolerate an air break between gate metal deposition and passivation. Fourth, the process should not involve highly reactive species which may damage different parts of the CMOS structure. Fifth, the process should utilize low cost and easy to maintain equipment. Sixth, the process should be suitable for batch processing (i.e. multiple wafers).
Passivation performed using a hydrogen plasma would not satisfy criteria four through six, highlighting a significant drawback of this technique.
BRIEF SUMMARY OF THE INVENTION
A new process for passivation of metal-gated CMOS structures has now been discovered which satisfies all the criteria described in the previous section. The new process may be implemented by two related procedures. Procedure 1 includes the steps of disposing a metal-gated CMOS structure in a chamber; removing the ambient air from chamber by evacuating that chamber to provide a high vacuum of 10
−5
Torr; introducing molecular hydrogen into the chamber so that hydrogen is present in a concentration such that the pressure in the chamber is at least about 200 Torr; concurrently heating the metal-gated CMOS structure to a temperature in the range of between about 250° C. and about 500° C.; cooling the CMOS structure in hydrogen; and removing the CMOS under ambient conditions. Procedure 2 includes the steps of disposing a metal-gated CMOS structure in a chamber; removing the ambient air from chamber by purging with an inert gas, such as nitrogen or argon, at atmospheric pressure or slightly above atmospheric pressure to reduce the partial pressure of ambient air. Specifically, oxygen, in the ambient air, is reduced to a concentration of less than about 20 parts per million (ppm); introducing molecular hydrogen into the chamber at atmospheric pressure so that the partial pressure of hydrogen is at least about 200 Torr; concurrently heating the metal-gated CMOS structure to a temperature in the range of between about 250° C. and about 500° C.; and removing the CMOS under ambient conditions.
REFERENCES:
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patent: 6410456 (2002-06-01), Gronet et al.
patent: 2002/0076886 (2002-06-01), Rotondaro et al.
K.L. Brower, “Passivation of Paramagnetic SI-SIO Interface States with Molecular Hydrogen”; Appl. Phys. Lett., 53 (6) p. 508-510 (1988).
K.L. Brower, “Dissociation Kinetics of Hydrogen-Passivated (111) SI-SIO Interface Defects”; U.S. Government, 42 (6) p. 3444-3456 (1990).
H. Shang et al., “Interface Studies of Tungstan Gate Metal-Oxide-Silicon Capacitors”Appl. Phys. Lett., 78 (20) p. 3139-3141 (2001).
A. Stesmans et al., “Hydrogen-Induced Thermal Interface Degradation in (111) Si/Sio Revealed by Electron-Spin Resonance”; Appl. Phys. Lett., 72 (18) p. 2271-2273.
Callegari Alessandro Cesare
D'emic Christopher P.
Kim Hyung-jun
McFeely Fenton Read
Narayanan Vijay
Coleman W. David
Scully Scott Murphy & Presser
Trepp Robert M.
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