Process of packaging an integrated circuit with a conductive mat

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438124, 438127, H01L 2156, H01L 2158, H01L 2160

Patent

active

058405992

ABSTRACT:
A process for manufacturing a lead frame (10) connected over an integrated circuit (40) by adhesives (42) and (44). Each lead conductor (16) and (18) of the lead frame (10) has the identical geometric area in order to provide identical capacitances. A metal shield may be provided on adhesives (42) and (44) to provide noise shielding for the integrated circuit (40).

REFERENCES:
patent: 3257588 (1966-06-01), Mueller
patent: 4514750 (1985-04-01), Adams
patent: 4551747 (1985-11-01), Gilbert et al.
patent: 4594641 (1986-06-01), Hernandez
patent: 4633583 (1987-01-01), Kato
patent: 4680613 (1987-07-01), Daniels et al.
patent: 4684975 (1987-08-01), Takiar et al.
patent: 4704187 (1987-11-01), Fujita
patent: 4711700 (1987-12-01), Cusack
patent: 4727221 (1988-02-01), Saitou
patent: 4733292 (1988-03-01), Jarvis
patent: 4743956 (1988-05-01), Olla et al.
patent: 4754317 (1988-06-01), Comstock et al.
patent: 4774635 (1988-09-01), Greenberg et al.
patent: 4803540 (1989-02-01), Moyer et al.
patent: 4803544 (1989-02-01), Holzschuh et al.
patent: 4820658 (1989-04-01), Gilder et al.
patent: 4862245 (1989-08-01), Pashby et al.
patent: 4868635 (1989-09-01), Fechette et al.
patent: 4872260 (1989-10-01), Johnson et al.
patent: 4876587 (1989-10-01), Hilton et al.
patent: 4916519 (1990-04-01), Ward
patent: 4953002 (1990-08-01), Nelson et al.
patent: 4953007 (1990-08-01), Erdos
patent: 4965654 (1990-10-01), Karner et al.
patent: 5089876 (1992-02-01), Ishioka
patent: 5233220 (1993-08-01), Lamson et al.
patent: 5338897 (1994-08-01), Tsay et al.
Ward, W. C., Volume Production of Unique Plastic Surface-Mount Modules for the IBM 80-ns 1-Mbit DRAM Chip by Area Wire Bond Techniques, Proceedings of the IEEE 1988 Electronic Components Conference, 1988, New York, pp. 552-557.
Chilo, J. T. Razban, Time Domain Performance on Advanced Packaging For High Speed ICs on GaAs, Proceedings of the 18th European Microwave Conference, Turnbridge Wells, GB, pp. 222-227.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Process of packaging an integrated circuit with a conductive mat does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process of packaging an integrated circuit with a conductive mat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process of packaging an integrated circuit with a conductive mat will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1701340

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.