Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-11-07
2002-10-29
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S435000, C438S437000, C438S424000, C438S692000
Reexamination Certificate
active
06472292
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese patent application No. 2000-367444 filed on Dec. 1, 2000, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device characterized by a process of forming a device isolation region of a integrated circuit.
2. Description of Related Art
According to recent high integration of semiconductor devices, miniaturization of devices and device isolation regions is being carried out.
The device isolation regions are formed by a trench device isolation technique including the steps of forming trenches in a surface of a semiconductor substrate, forming an insulating film to fill the trenches, and flattening the insulating film.
Such a technique may be suitable for the miniaturization of the device isolation regions. However, if the device isolation regions are formed at a level lower than that of the semiconductor surface, an electric field is concentrated at a channel boundary of the transistor and a hump current is generated.
In view of such a problem, Japanese Unexamined Patent Publication No. Hei 11(1999)-26571 proposes a method of preventing the device isolation regions from being formed below a surface of a silicon substrate. The method is detailed below referring to
FIGS. 2 and 3
.
First, an oxide film
202
of about 100Å thick is formed on a silicon substrate
201
by oxidation diffusion and then a nitride film
203
of about 2000Å thick is formed thereon by known CVD as shown in FIG.
2
A. Then, the nitride film
203
is patterned by known photolithography and anisotropic etching as shown in
FIG. 2B
such that the oxide film
202
is exposed in a device isolation region-to-be. With the thus patterned nitride film
203
as a mask, the oxide film
202
is etched and the silicon substrate
201
is also etched to form a trench
204
for device isolation with a depth of about 0.2-0.7 &mgr;m as shown in FIG.
2
C. The nitride film
203
is then isotropically etched in a hot phosphoric acid solution such that the nitride film
203
is isotropically reduced from each sidewall of the trench, i.e., from the position indicated by the broken line shown in
FIG. 2D
, towards the center of a region for forming a transistor by about 500Å. The silicon substrate
201
is oxidized to form an oxide film
205
of about 150Å thick at the bottom and sides of the trench
204
as shown in FIG.
2
E. Then, an oxide film
206
of about 0.4-1.0 &mgr;m is deposited by CVD as shown in FIG.
2
F. The oxide film
206
is flattened by CMP (Chemical Mechanical Polishing) until the nitride film
203
is exposed as shown in FIG.
2
G. The nitride film
203
is removed in a hot phosphoric acid solution as shown in
FIG. 2H
, and then the oxide film
202
is removed to complete the trench device isolation structure as shown in FIG.
21
.
According to such a technique, the top surface of the device isolation region is prevented from being located below the silicon substrate surface, which allows avoiding the generation of the hump current.
However, on a large active region
301
and an isolated small active region
302
as shown in
FIG. 3A
, the oxide film
206
is deposited at different density. When the oxide film
206
is flattened, it is polished at different polishing rate between the large active region
301
and the isolated small active region
302
. As a result, the oxide film remains on the large active region
301
as indicated by reference numeral
303
shown in
FIG. 3B
, which hinders the nitride film
203
from being completely removed in a later step. Even if the oxide film
206
is polished for a longer period so that the remain
303
of the oxide film is completely removed, the nitride film
203
on the isolated small active region
302
is greatly polished, and the underlying active region
302
may possibly be polished. Thus, in this method, it is difficult to estimate the optimum amount to be polished. Further, as shown in
FIG. 3C
, the level of the buried oxide film
206
and that of the silicon substrate
201
are significantly different, which causes focus offset in the lithography step for patterning a gate electrode wiring
304
. Moreover, since a thickness of the gate electrode wiring
304
increases on the step portion, the wiring
304
is not fully etched away and remains as indicated by reference numeral
305
as shown in
FIG. 3D
, which causes short circuit between the electrodes.
SUMMARY OF THE INVENTION
In view of the above problems, an object of the present invention is to provide a method of manufacturing a semiconductor device, the method capable of preventing the oxide film on the active regions from remaining due to the difference in polishing rate depending on the difference in dimension of the underlying active regions, and reducing the level difference between the device isolation region and the active region which causes the focus offset in the lithography step for patterning the gate electrode wiring and the incomplete removal of the wiring.
The inventor of the present invention has found that the above-mentioned problems are solved by removing the remain of the insulating film on the active regions generated due to the difference in polishing rate depending on the difference in dimension of the underlying active region and simultaneously reducing the insulating film buried in the trench.
According to the present invention, provided is a method of manufacturing a semiconductor device including a plurality of active regions of different area and device isolation regions formed between the active regions, the method comprising the steps of: forming a first insulating film and a second insulating film in sequence on a semiconductor substrate; forming a plurality of openings through the first and second insulating films at desired positions; forming trenches in the semiconductor substrate in the openings to define active regions of different area and device isolation regions between the active regions; depositing a third insulating film on the semiconductor substrate so that the trenches are filled with the third insulating film; flattening the third insulating film by CMP until the second insulating film is exposed in the active regions; and removing the third insulating film remaining in the active regions because of a difference in polishing rate derived from variation in deposit density in the third insulating film and simultaneously reducing the third insulating film in the trenches.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 5702977 (1997-12-01), Jang et al.
patent: 5719085 (1998-02-01), Moon et al.
patent: 6242352 (2001-06-01), Chen et al.
patent: 6294470 (2001-09-01), Economikos et al.
patent: 6335287 (2002-01-01), Hwang et al.
patent: 6391792 (2002-05-01), Jang et al.
patent: 6403483 (2002-06-01), Hao et al.
patent: 11-26571 (1999-01-01), None
Dang Trung
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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