Process of manufacturing compliant wirebond packages

Details Process of manufacturing compliant wirebond packages Process of manufacturing compliant wirebond packages

1997-12-12

1999-11-23

Graybill, David E.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Incorporating resilient component

438124, 438126, 438127, 438617, 438977, H01L 21283, H01L 2156, H01L 2158, H01L 2160

Patent

active

059899395

ABSTRACT:
A method of making a assembly including the steps of fitting a chip within an aperture in a frame, connecting the bond pads on the frame to the contacts on the chip by forming wire loops therebetween, dispensing a compliant material over the frame, chip and wire loops for form a compliant layer, and plasma etching the top surface of the compliant layer to expose the top portion of each wire loop. The semiconductor chip assembly can then be incorporated into a larger assembly by connecting the wire loops to connection pads on an external substrate.

REFERENCES:
patent: 4764848 (1988-08-01), Simpson
patent: 5148265 (1992-09-01), Khandros et al.
patent: 5148266 (1992-09-01), Khandros et al.
patent: 5455390 (1995-10-01), DiStefano et al.
patent: 5476211 (1995-12-01), Khandros
patent: 5801446 (1998-09-01), DiStefano et al.
patent: 5806181 (1998-09-01), Khandros et al.
patent: 5829128 (1998-11-01), Eldridge et al.

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