Process of making twin well VLSI CMOS

Details Process of making twin well VLSI CMOS Process of making twin well VLSI CMOS

1984-06-15

1986-07-15

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 148 15, 148187, 156643, 357 42, 357 91, H01L 21265, B01J 1700

Patent

active

045997896

ABSTRACT:
CMOS devices are formed in self-aligned wells in a substrate produced by a two mask, one photolithographic step process wherein the first mask is used as a template to form the second inverse mask of substantially equal thickness. The gates are used as alignment mask for shallow source and drain regions and subsequently formed lateral gate spacers are used as alignment mask for deep source and drain regions. Exposed source and drain regions and silicon gates have silicide formed thereon by a non-selective process.

REFERENCES:
patent: 3759763 (1973-09-01), Wang
patent: 4209350 (1980-06-01), Ho et al.
patent: 4280272 (1981-07-01), Egawa et al.
patent: 4319395 (1982-03-01), Lund et al.
patent: 4333099 (1982-06-01), Tanguay et al.
patent: 4343082 (1982-08-01), Lepselter et al.
patent: 4356040 (1982-10-01), Fu et al.
patent: 4356623 (1982-11-01), Hunter
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4385947 (1983-05-01), Halfacre et al.
patent: 4411058 (1983-10-01), Chen
patent: 4420344 (1983-12-01), Davies
patent: 4434543 (1984-03-01), Schwabe et al.
patent: 4435896 (1984-03-01), Parrillo et al.
patent: 4442591 (1984-04-01), Haken
patent: 4444605 (1984-04-01), Slawinski
patent: 4453306 (1984-06-01), Lynch et al.
"Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology"; Tsang et al.; IEEE; vol. ED-29, No. 4, Apr. 1982, pp. 590-596.
"An Optimally Designed Process for Submicrometer MOSFET's"; Shibata et al.; IEEE, vol. ED-29, No. 4, Apr. 1982, pp. 531-535.
"Twin-Tub CMOS--A Technology for VLSI Circuits"; Parrillo et al.; IEDM, 1980, pp. 752-755.
"Twin-Tub CMOS II--An Advanced VLSI Technology"; Parrillo et al.; IEDM 1982, pp. 706-709.
"Quadruple-Wall CMOS--A VLSI Technology"; Chen; IEDM 1982, pp. 791-792.

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