Process of making EEPROM memory device having a sidewall spacer

Details Process of making EEPROM memory device having a sidewall spacer Process of making EEPROM memory device having a sidewall spacer

1995-05-23

1996-02-27

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 44, 437 49, H01L 218247

Patent

active

054948380

ABSTRACT:
An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (2) from the source region (12). The control gate electrode (20) overlies a third channeI region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.

REFERENCES:
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Yamauchi, et al., "A 5V-Only Virtual Ground Flash Cell with an Auxiliary Gate for High Density and High Speed Application", IEEE Sep. 1991, pp. 319-322.

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