Process of making a semiconductor device having parallel leads d

Details Process of making a semiconductor device having parallel leads d Process of making a semiconductor device having parallel leads d

1984-09-27

1986-10-14

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29589, 29590, 29591, 357 68, 357 72, 357 74, 174 52PE, H01L 2302, H01L 2348, H01L 2328

Patent

active

046164065

ABSTRACT:
An improved package for a semiconductor device comprises an integrated circuit die and a mounting package having an array of parallel leads which directly connect perpendicular to the die. The process for making the package comprises forming an array of parallel, spaced apart, conductor pins; bonding the array of parallel conductor pins directly to an integrated circuit die while maintaining the die in a plane perpendicular to the parallel pins; and surrounding the die with a package material capable of protecting the die.

REFERENCES:
patent: 3273029 (1966-09-01), Ross
patent: 4074342 (1978-02-01), Honn et al.
patent: 4196444 (1980-04-01), Butner et al.
patent: 4312116 (1982-01-01), Moser et al.
patent: 4407007 (1983-09-01), Desai et al.
patent: 4451842 (1984-05-01), Pommerrenig
Blodgett, Jr., A. J., "Microelectronic Packaging" in Scientific American, vol. 249 No. 1, Jul. 1983, pp. 86-96.

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