Process of making a planar MOS silicon-on-insulating substrate d

Details Process of making a planar MOS silicon-on-insulating substrate d Process of making a planar MOS silicon-on-insulating substrate d

1978-08-10

1979-12-11

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148187, 357 23, 357 49, 357 52, 357 91, H01L 21225, H01L 21263, H01L 1100

Patent

active

041781910

ABSTRACT:
An improved process of forming planar silicon-on-sapphire MOS integrated circuit devices by a local oxidation process in which portions of a silicon layer on a sapphire substrate are thermally oxidized throughout the thickness of the layer to provide interdevice dielectric isolation and a substantially planar topology includes a step of ion implanting phosphorus, boron, or a combination thereof into the silicon prior to the thermal oxidation step. The implanted impurities have a stabilizing effect on the devices thereafter built in the remaining silicon.

REFERENCES:
patent: 3890632 (1975-06-01), Ham et al.
patent: 4081292 (1978-03-01), Aoki et al.
patent: 4098618 (1978-07-01), Crowder et al.
Rideout "Reducing Laterel Oxidation . . .", IBM-TDB, 18 (1975), 1616.
Nomura et al., "Enhanced Oxidation of Si . . .", Ion-Implantation in Semiconductor, S. Hambe, Plenum, 1974, p. 681.
Bhatia et al., "Isolation Process for Shallow Tunction . . .", IBM-TDB, 19 (1977), 4171.
Shamakura et al., "B and P Diffusion . . . SiO.sub.2 . . .", Solid State Electronics, 18 (1975), 991.
Prince et al., "Diffusion of B from Implanted Source . . .", J. Electrochem. Soc. 121 (1974), 705.
Capell et al., ". . . C-MOS on Sapphire . . .", Electronics, May 1977, p. 99.
Fritzes et al., "Thermal Oxidation of Si . . . ", J. Electrochem. Soc. 120 (1973), 1603.
Hess et al., ". . . Oxidation . . . Ion-Implantation . . .", J. Appl. Phys. 48 (1977), 834.
Christodoulides et al., ". . . Ion Implanted, . . . Oxidized Si", J. Electrochem. Soc. 124 1977, 1651.

Affiliated with

Also associated with

Rating

Process of making a planar MOS silicon-on-insulating substrate d does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process of making a planar MOS silicon-on-insulating substrate d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process of making a planar MOS silicon-on-insulating substrate d will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-309327