Process of forming miniature pattern well controlled in thicknes

Details Process of forming miniature pattern well controlled in thicknes Process of forming miniature pattern well controlled in thicknes

1995-09-19

1997-10-21

Gorgos, Kathryn

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Coating selected area

205124, 205157, 205159, 205164, 205165, 205166, 205167, 205189, 205186, 205187, 205188, 20419234, 437228M, 437228I, 437 40GS, 437 41GS, 437230, 437246, C25D 502, C25D 554, C25D 2802, H01L 21465

Patent

active

056792344

ABSTRACT:
A mask layer is formed on a conductive layer covering not only a central area assigned to integrated circuits but also a vacant peripheral area of a semiconductor wafer, and an electroplating system allows metallic miniature patterns to grow on the conductive layer over the vacant peripheral area as well as extremely small areas of the conductive layer over the central area so as to make current fluctuation negligible.

REFERENCES:
patent: 4897361 (1990-01-01), Harriott et al.
patent: 4963512 (1990-10-01), Iwanaga et al.
patent: 5296399 (1994-03-01), Park
IBM Technical Disclosure Bulletin, vol. 31, No. 6, p. 488, Nov. 1988.
Reinken, "Rectifiers", Electroplating Engineering Handbook, 2nd ed., pp. 666-673, ?1962.

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