Process of forming input/output wiring areas for semiconductor i

Details Process of forming input/output wiring areas for semiconductor i Process of forming input/output wiring areas for semiconductor i

1986-02-12

1988-10-18

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 51, 437204, 324158T, G01R 3126

Patent

active

047787716

ABSTRACT:
A process of fabricating a semiconductor integrated circuit wherein a plurality of device-forming areas are formed on a semiconductor wafer, whereupon, interconnection wiring patterns are formed on the device-forming areas, respectively, so that each of the device-forming areas and the interconnection wiring pattern on the particular device-forming area form an incomplete integrated circuit portion. Each of the incomplete integrated circuit portions is then inspected for defects in functions and capabilities thereof, whereupon input/output terminal wiring patterns are formed only for those of the incomplete integrated circuit portions which have been determined to be acceptable as a result of the inspection step.

REFERENCES:
patent: 3795973 (1974-03-01), Calhoun
patent: 3795975 (1974-03-01), Calhoun et al.
patent: 3849872 (1974-11-01), Hubacher
patent: 3940740 (1976-02-01), Coontz
patent: 3981070 (1976-09-01), Buelow et al.
patent: 4104785 (1978-08-01), Shiba et al.
patent: 4243937 (1981-01-01), Multani et al.
patent: 4691434 (1987-09-01), Percival et al.

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