Process of forming breadboard interconnect structure having plat

Details Process of forming breadboard interconnect structure having plat Process of forming breadboard interconnect structure having plat

1987-10-05

1989-05-30

Beck, Shrive

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

427 98, 427 97, B05D 512

Patent

active

048350087

ABSTRACT:
A process for forming an interconnect structure atop an insulated circuit board comprises selectively forming a first metallic (copper) layer on a first surface of an insulator (Teflon) board, so as to define the intended geometry of a pattern of interconnect metal. Atop this structure a buffer layer of photoresist is non-selectively formed and then apertures are drilled through selected locations in the buffer layer and underlying metallic layer and insulator board. Next, the resulting structure is plated with a second metallic layer, so as to coat the buffer layer and sidewalls of the apertures with a metallic plating. Finally, a photoresist wash is applied to cause the buffer layer to be dissolved and its coating of metallic plating to be lifted off the insulator board and the first metallic layer. Since the original geometry of the interconnect line pattern has been protected during through-hole formation and electroplating its electrical characteristics remain unaltered. When the buffer layer of protective photoresist is dissolved the electroplate simply lifts off the board away from the plated through-holes and built-up interconnect, thereby leaving the pattern of interconnect metal and the coating of metallic plating in the apertures intact.

REFERENCES:
patent: 3457638 (1969-07-01), Johnson
patent: 3672986 (1972-06-01), Schneble
patent: 4206254 (1980-06-01), Schmeckenbecher
patent: 4224361 (1980-09-01), Romankiw
patent: 4377316 (1983-03-01), Ecker
patent: 4388351 (1983-06-01), Sawyer
patent: 4526810 (1985-07-01), Nesbitt
patent: 4606787 (1986-08-01), Pelligrino

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