Process of fabricating TiW/Si self-aligned gate for GaAs MESFETs

Details Process of fabricating TiW/Si self-aligned gate for GaAs MESFETs Process of fabricating TiW/Si self-aligned gate for GaAs MESFETs

1985-06-06

1987-12-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

357 15, 357 71, 357141, H01L 21283

Patent

active

047122919

ABSTRACT:
A major difficulty with fabricating GaAs digital logic circuits using enhancement-mode MESFETs has been the large gate-source and gate-drain parasitic resistances inherent in conventional designs. A self-aligned gate process is presented, which incorporates a "mushroom" gate structure for self-aligning both an n+ implant and the source/drain contacts to the gate, thus minimizing the parasitic resistances. The "mushroom" gate consists of a two-layer TiW/Si metallization in which the bottom TiW layer is undercut with a closely controllable chemical etch. The process is compatible with the high temperature anneal necessary to activate ion-implanted GaAs.

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