Process of fabricating semiconductor device involving planarizat

Details Process of fabricating semiconductor device involving planarizat Process of fabricating semiconductor device involving planarizat

1987-07-09

1988-05-24

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 31, 437228, 437233, 148DIG11, 357 34, H01L 21225, H01L 21385

Patent

active

047466294

ABSTRACT:
A process of fabricating a semiconductor device comprising the steps of forming a dielectric layer overlying a doped semiconductor layer, forming a first insulator layer on the dielectric layer, etching the dielectric layer and the insulator layer to form a bump region comprising coextensively patterned portions of the dielectric and insulator layers, forming a second insulator layer partly on the doped semiconductor layer and partly on the bump region, conformally forming on the second insulator layer an undoped polycrystalline semiconductor layer having a step portion, forming on the polycrystalline semiconductor layer a planarizing layer covering the step portion of the polycrystalline semiconductor layer, etching back the polycrystalline semiconductor layer and the planarizing layer until the second insulator layer has a surface portion exposed over the bump region, etching the first and second insulator layers with the remaining portion of the polycrystalline semiconductor layer used as a mask for forming an opening in part extending to the surface of the dielectric layer and having a marginal groove portion extending to the surface of the doped semiconductor layer, and thereafter forming various desired device regions through and in alignment with this opening.

REFERENCES:
patent: 4252582 (1981-02-01), Anantha et al.
patent: 4274909 (1981-06-01), Venkataraman et al.
patent: 4378630 (1983-04-01), Horng et al.
patent: 4545114 (1985-10-01), Ito et al.
patent: 4693782 (1987-09-01), Kikuchi et al.

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