Process of fabricating complementary inverter circuit having mul

Details Process of fabricating complementary inverter circuit having mul Process of fabricating complementary inverter circuit having mul

1994-08-16

1995-05-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

257371, 257384, 257754, 257770, 437 34, 437 56, 437200, 437193, 148DIG19, 148DIG147, H01L 2170

Patent

active

054181798

ABSTRACT:
An integrated circuit is fabricated on a semiconductor substrate and comprises an n channel type field effect transistor, a p channel type field effect transistor and an interconnection coupled between the drain regions of the two field effect transistors, and each of the gate electrodes and the interconnection is provided with a polycrystalline silicon and a refractory metal silicide deposited over the polycrystalline silicon, wherein side spacers are eliminated from the gate electrodes and the interconnection, because no short circuiting takes place between the gate electrodes and the source and drain regions by virtue of the deposition of the refractory metal silicide.

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