Process of fabricating an insulated-gate field effect transistor

Details Process of fabricating an insulated-gate field effect transistor Process of fabricating an insulated-gate field effect transistor

1992-02-25

1994-02-22

Quach, T. N.

Fishing, trapping, and vermin destroying

437 29, 437 40, 437911, 148DIG126, H01L 21336

Patent

active

052886530

ABSTRACT:
A process of fabricating an insulated-gate field effect transistor includes step for forming a silicon gate electrode 5 on a gate insulation film 4 deposited over one surface of a p-type semiconductor substrate 10; forming n-type base regions 7 extending beneath the silicon gate electrode by introducing an n-type impurity into specified areas of the surface of the semiconductor substrate using the silicon gate electrode 5 as a mask, and then laterally diffusing the introduced impurity; forming a mask layer 8 on the silicon gate electrode; forming p-type source regions in the base regions 7 by introducing p-type impurity, with the silicon gate electrode 5 masked with the mask layer 8, into the specified areas of the surface of the semiconductor substrate, thereby portions in the base regions 7 beneath the silicon gate electrode 5 being defined as channel regions 12; forming a drain electrode 14 on the other surface of the semiconductor substrate 10. This process allows substantially only one impurity of the conductivity type (n-type in this case) to enter in the silicon gate electrode, thus contributing to making the resistance of this silicon gate electrode lower.

REFERENCES:
patent: 4680853 (1987-07-01), Lidow et al.
patent: 4798810 (1989-01-01), Blanchard et al.
patent: 5141883 (1992-08-01), Ferla et al.
Wolf, et al., Silicon Processing, vol. I, Process Technology, 1986, Lattice Press, pp. 302-309, 314-327.

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