Process of fabricating an antifuse structure

Details Process of fabricating an antifuse structure Process of fabricating an antifuse structure

1997-12-30

1999-06-22

Niebling, John F.

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to conductive state

438467, 438600, 257530, H01L 2182

Patent

active

059151714

ABSTRACT:
An antifuse structure for semiconductor programmable logic devices and the process of fabrication are described. The antifuse structure has its bottom electrically conductive layer featuring sharp corners formed by consumption of the polysilicon material into the sidewall in a thermal oxidation procedure. The sharp corners enhance the intensity of electric field established by a positive bias applied across the top and bottom conductive layers. The sharp corners do not enhance the electric field intensity when a negative bias is applied. This asymmetric conductivity assists in the reduction of the programming voltage as well as the increase of programming speed when the antifuse element is programmed.

REFERENCES:
patent: 5290734 (1994-03-01), Boardman et al.
patent: 5726483 (1998-03-01), Dennison
patent: 5756393 (1998-05-01), Dennison

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