Process of fabricating a semiconductor substrate with...

Details Process of fabricating a semiconductor substrate with... Process of fabricating a semiconductor substrate with...

1998-05-15

2001-04-24

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Gettering of substrate

By layers which are coated, contacted, or diffused

C438S476000, C438S471000, C438S058000

Reexamination Certificate

active

06221741

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor wafer and a process of fabrication thereof and, more particularly, to a semiconductor wafer with a gettering site layer of semi-insulating polycrystalline silicon and a process of fabrication thereof.
DESCRIPTION OF THE RELATED ART
A semiconductor device has been enhanced in integration density. An integrated circuit is concurrently fabricated on a large diameter silicon wafer, and the device fabrication technology becomes complicated. An appropriate gettering technique is required for semiconductor devices in the next generation.
The denuded zone intrinsic gettering is a typical gettering technology for a silicon wafer. However, the denuded zone intrinsic gettering process requires long heat treatment for a large diameter silicon wafer, and the long heat treatment is costly.
A poly-back seal gettering is a kind of extrinsic gettering technology, and a polycrystalline silicon layer is formed on the back surface of a silicon wafer. The gettering efficiency of the polycrystalline silicon layer is dependent on the depositing conditions of polycrystalline silicon. The optimization of gettering efficiency is taught by D. M. Lee et. al. in “IRON GETTERING EFFICIENCY BY A POLYSILICON LAYER IN P-TYPE CZ SILICON”, Journal of Electrochemical Society, pages 820 to 830, 1994.
FIG. 1
illustrates a semiconductor structure used in the experiments carried out by D. M. Lee et. al. The semiconductor structure consists of a single crystalline silicon layer
1
and a polycrystalline silicon layer
2
grown on the back surface of the single crystalline silicon layer
1
. The single crystalline silicon layer
1
is grown through a Czochalski crystal growing technology, and the polycrystalline silicon layer
2
is grown under different conditions.
The polycrystalline silicon layer
2
of the first sample is grown to 0.8 micron thick at 700 degrees centigrade, the polycrystalline silicon layer
2
of the second sample is grown to 1.2 microns thick at 700 degrees centigrade, the polycrystalline silicon layer
2
of the third sample is grown to 1.6 microns thick at 700 degrees centigrade, and the polycrystalline silicon layer 2 of the fourth sample is grown to 1.2 microns thick at 620 degrees centigrade. Comparative samples are prepared through different gettering treatments. The first comparative sample is treated with etching instead of the deposition of polycrystalline silicon, and the second comparative sample is treated with sand blasting instead of the deposition of polycrystalline silicon. The six samples, i.e., the first sample to the fourth sample, the first comparative sample and the second comparative sample are contaminated with iron, and, thereafter, the residual iron is measured.
FIG. 2
illustrates the residual iron concentration, and
FIG. 3
shows a series of microphotographs Sections A, B, C and D show the crystal structure of the second comparative sample, the crystal structure of first sample, the crystal structure of the second sample and the crystal structure of the third sample, respectively. As will be understood from
FIG. 2
, the thicker the polycrystalline silicon layer
2
is, the larger the gettering efficiency is 1.2 microns is the minimum thickness of the polycrystalline silicon layer
2
effective against the iron. Moreover, the low deposition temperature makes the crystal grain of the polycrystalline silicon small, and the small crystal grain reduces the gettering efficiency. The deposition around 700 degrees centigrade is appropriate. The microphotographs teach that high-dense twin crystal takes place during the solid state growth in the thin polycrystalline silicon layer such as the first sample. On the other hand, a large amount of grain boundary is left in the thick polycrystalline silicon layer such as the third sample after the CMOS heat treatment, and still has good gettering capability. Thus, the gettering efficiency is optimized by controlling the deposition temperature and the deposition time.
As taught by D. M. Lee, the large gettering efficiency requires the polycrystalline silicon of at least 1.2 microns thick, and the thick polycrystalline silicon layer
2
tends to warp the single crystalline silicon wafer
1
. This is the first problem inherent in the prior art poly-back seal technology.
Another problem is that the gettering efficiency is reduced in a heat treatment repeated during a fabrication process of a semiconductor device. As described hereinbefore, much grain boundary achieves large gettering efficiency. However, the heat treatment promotes the solid phase growth in the polycrystalline layer
2
, and the polycrystalline silicon layer loses the gettering capability. In order to restrict the solid phase growth from poly-crystal to single crystal, Japanese Patent Publication of Unexamined Application No. 1-235242 proposes an ion implantation of impurity serving as an inhibitor against the solid phase growth into a back surface portion of a single crystalline silicon wafer. The ion-implantation is carried out before the deposition of polycrystalline silicon on the back surface of the single crystalline silicon wafer, and nitrogen, oxygen and argon are examples of the inhibitor. The inhibitor prevents the polycrystalline silicon layer from decreasing thickness during a fabrication process for an integrated circuit. Thus, the inhibitor is effective against the heat treatment in the fabrication process of an integrated circuit. However, large gettering efficiency still requires the polycrystalline silicon layer equal to or greater than 1.2 microns thick, and the thick polycrystalline silicon layer is causative of the warp undesirably produced in the single crystalline silicon wafer.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a semiconductor substrate, which achieve good gettering efficiency without serious warp.
It is also an important object of the present invention to provide a process of fabricating the semiconductor substrate.
To accomplish the object, the present invention proposes to form a gettering site layer of semi-insulating polycrystalline silicon containing oxygen at least 10 percent by weight. The semi-insulating polycrystalline silicon contains oxygen at least ten percent by atom.
In accordance with one aspect of the present invention, there is provided a semiconductor substrate used for fabrication of a semiconductor device comprising an active layer formed of single crystalline semiconductor material and having a first surface used for fabricating at least one electric component thereon and a second surface reverse to the first surface, and a gettering site layer grown on the second surface of the active layer and formed of semi-insulating polycrystalline silicon containing oxygen of at least 10 percent by atom.
In accordance with another aspect of the present invention, there is provided a process of producing a semiconductor substrate used for a semiconductor device comprising the steps of preparing an active layer of single crystalline semiconductor material, and forming a gettering site layer formed of semi-insulating polycrystalline silicon containing oxygen of at least 10 percent by atom on one surface of the active layer.


REFERENCES:
patent: 3997368 (1976-12-01), Petroff et al.
patent: 4053335 (1977-10-01), Hu
patent: 4608096 (1986-08-01), Hill
patent: 4803528 (1989-02-01), Pankove
patent: 55-15286 (1980-02-01), None
patent: 59-186331 (1984-10-01), None
patent: 1-235242 (1989-09-01), None
patent: 5-136153 (1993-06-01), None
patent: 6-216137 (1994-08-01), None
patent: 7-29911 (1995-01-01), None
D.M. Lee et al., “Iron Gettering Efficiency By A Polysilicon Layer In P-Type CZ Silicon”,Journal of Electrochemical Society, 1994, pp. 820-830.

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