Process of fabricating a semiconductor IC involving simultaneous

Fishing – trapping – and vermin destroying

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437238, 20419237, H01L 21465

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active

047496630

ABSTRACT:
In a process of fabricating a semiconductor IC having a plurality of metal wiring conductor layers on a semiconductor substrate and an insulation layer between the metal wiring conductor layers, the insulation layer being formed of a silicon oxide film is formed by means of RF bias-sputtering, a silicon oxide film is formed by means of RF bias sputtering under such a condition that the deposition rate and the etching rate on a pattern surface 45.degree. inclined with respect to the reference surface of the semiconductor substrate are equal, part of the silicon oxide film over the underlying metal wiring conductor layer being protruded; a trench is formed in part of the silicon oxide film covering the metal wiring conductor layer, and the silicon oxide is etched by RF bias sputtering under such a condition that the deposition rate and etching rate on a pattern surface parallel to the reference surface of the semiconductor substrate are equal, until the protrusion of the silicon oxide film over the metal wiring conductor is removed so that the entire silicon oxide film is planarized.

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patent: 4681653 (1987-07-01), Purdes et al.
patent: 4690746 (1987-09-01), McInerney et al.
Kotani et al, "Sputter Etching Planarization . . . ", J. Electrochem. Soc., vol. 130, No. 3, 4/83, pp. 645-648.

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