Process of fabricating a high capacitance storage node

Details Process of fabricating a high capacitance storage node Process of fabricating a high capacitance storage node

1993-02-03

1994-02-15

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 60, 437233, 437919, H01L 2170

Patent

active

052866688

ABSTRACT:
A method for the fabrication of high density dynamic random access memory (DRAM) devices with particular emphasis on the capacitor formation. The capacitor is formed using layers of doped and undoped polysilicon. The layers are patterned anisotropically so as to have their remaining portions over the planned capacitor areas, wherein a portion of the layers remains over both the gate structure and the field oxide areas. Then selective etching of the portion of doped polysilicon layer is accomplished using phosphoric acid at a temperature of more than abut 140.degree. C. to create an undercut of the undoped polysilicon layer. The capacitor is completed using a dielectric layer and a top electrode layer.

REFERENCES:
patent: 5071783 (1991-12-01), Taguchi et al.
patent: 5168073 (1992-12-01), Gonzalez et al.
patent: 5215930 (1993-06-01), Lee et al.

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